Advanced Logic Synthesis

TingTing Hwang (黄婷婷)

Announcement

Tools

Espresso

Description: 2-level heuristic minimizer

Release Date: 2023-03-07

Source Code

Executeble File

SIS

Description: Division Based Multi-level heuristic minimizer

Release Date: 2023-03-07

Executeble File

Supplementary Matarials:

SIS Tutorial 1

SIS Tutorial 2

SIS Detail Command 1

SIS Detail Command 2

ABC

Description: DAG-Aware Multi-level minimizer

Release Date: 2023-03-07

Source Code

Executeble File

SAT Attack Tool

Description: SAT Attack Tool for Logic decryption

Release Date: 2023-03-23

Source Code

Executeble File

Benchmark

Name: MCNC Benchmark

Release Date: 2023-03-19

Description

Download Set

Homework&Lab

FINAL: FSM State Assignment for Low Power Dissipation

Release Date: 2023/5/22

Deadline: 2023/6/21

Description: FINAL:Description

HW2: SAT Attack Report

Release Date: 2023/5/3

Deadline: 2023/5/22

Description: HW2:Description

HW1: SIS&ABC Report

Release Date: 2023/3/29

Deadline: 2023/4/17

Description: HW1:Description

Presentation
DATE Presenter Paper
5/24 何雨澂 An Approach to Unlocking Cyclic Logic Locking - LOOPLock 2.0
5/24 林祐丞 A Heuristic Boolean NPN Equivalent Matching Verification Method Based on Shannon Decomposition
5/24 王睿杰 Expanding In-Cone Obfuscated Tree For Anti SAT Attack
5/29 姜柏丞 Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF Formulations
5/29 王郁淇 Novel Probabilistic Combinational Equivalence Checking
5/29 劉和鑫 A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization
5/29 錢珈鋒 Fast Node Merging With Don't Cares Using Logic Implications
5/29 許子麗 Simulation and SAT-based Boolean matching for large Boolean networks
5/31 劉杰閎 Security-aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection Attacks
5/31 楊峻齊 Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation
5/31 賴亮宇 A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits
6/5 王領崧 Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) – Unlocked
6/5 蘇勇誠 Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications
6/5 陳冠宗 A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping
6/5 尤瑞辰 An MIG-based compiler for programmable logic-in-memory architectures
6/5 吳律穎 DAG-aware logic synthesis of datapaths
6/7 李俊毅 DRiLLS: Deep Reinforcement Learning for Logic Synthesis
6/7 林鼎勲 Reverse Engineering Camouflaged Sequential Circuits Without Scan Access
6/7 鄭翔駿 Enhanced Fast Boolean Matching based on Sensitivity Signatures Pruning

Outlines

0: Introduction
1: Representations for Boolean Functions

  • 1.1 Representations for Boolean Functions

    Release Date: 2023-02-14

    Download Slide

2: Two-Level Logic Minimization
3: Multi-Level Logic Minimization
4: Timing Optimization
5: Technology Mapping

  • 5.1 Technology Mapping

    Release Date: 2023-03-22

    Download Slide

  • 5.2 Boolean Matching in Logic Synthesis

    Release Date: 2023-03-22

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6: Finite State Machine
7: Low Power
8: Testing
9: Hardware Security