Advanced Logic Synthesis

CS 613200: Advanced Logic Synthesis

TingTing Hwang

NTHU

Announcements

2025-02-10

If you do NOT have an account on NTHU CAD Server, please apply it from: NTHU CAD Server

2025-02-25

Due to the teacher's illness, the class on February 26 (Wednesday) is canceled.

2025-03-31

Since the professor is attending an overseas conference today (March 31), today's class will be conducted by the teaching assistant, Mark Towne, who will be explaining some details and usage of SIS and ABC. The slides for today's presentation are attached: Introduce SIS & ABC

Course Materials

Chapter 0

Introduction

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0.1 Introduction

Release: 2025-02-11

Chapter 1

Representations for Boolean Functions

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1.1 Representations for Boolean Functions

Release: 2025-02-11

Chapter 2

Two-Level Logic Minimization

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2.1 Exact Minimization

Release: 2025-02-11

2.2 Heuristic Minimization

Release: 2025-03-03

2.3 Multiple Value Function

Release: 2025-03-07

Reference 1: Expand

Release: 2025-03-07

Reference 2: Irredundant Cover

Release: 2025-03-07

Reference 3: Reduce

Release: 2025-03-07

Chapter 3

Multi-Level Logic Minimization

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3.1 Multiple Level Logic Restructure

Release: 2025-03-11

3.2 Node Optimization

Release: 2025-03-11

3.3 Multi-Level AIG Rewriting

Release: 2025-03-11

3.4 Functional Decomposition

Release: 2025-03-11

Chapter 4

Timing Optimization

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4.1 Timing Optimization

Release: 2025-03-26

Chapter 5

Technology Mapping

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5.1 Technology Mapping

Release: 2025-04-09

5.2 Boolean Matching in Logic Synthesis

Release: 2025-04-14

Chapter 6

Synthesis for Finite State Machines

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6.1 Finite State Machine

Release: 2025-04-14

Chapter 7

Low Power Design

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7.1 Logic Synthesis For Low Power CMOS Digital Design

Release: 2025-04-28

Chapter 8

Automatic test pattern generation & Logic optimization

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8.1 Automatic Test Generation and Logic Optimization

Release: 2025-04-28

8.2 False Path Identification

Release: 2025-04-28

Chapter 9

Hardware Security

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9.1 Hardware Security

Release: 2025-05-07

Homework

HW1: ABC & SIS Report

Release Date: 2025-03-24 Due: 2025-04-09

HW1 Description

HW2: SAT Attack Report

Release Date: 2025-05-14 Due: 2025-05-22

HW2 Description

Final Project: LUT Mapping

Release Date: 2025-05-20 Due: 2025-06-13

Final Project Description | Final Project File

Tools

Espresso

2-level heuristic minimizer

Release : 2025-02-10

Source Code Executable File

SIS

Division Based Multi-level minimizer

Release: 2025-02-10

Executable File

Supplementary Materials:

Tutorial 1 Tutorial 2 Command Guide 1 Command Guide 2

ABC

DAG-Aware Multi-level minimizer

Release: 2025-02-10

Source Code Executable File

SAT Attack Tool

Oracle-guided Attack

Release: 2025-05-14

Source Code Executable File

Benchmark

MCNC Benchmark

Release: 2025-02-10

Presentation

2025-05-02 (Wed) [1]

Improving Standard-Cell Design Flow using Factored Form Optimization

徐義鈞

2025-05-02 (Wed) [2]

Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm

吳宗喬

2025-05-02 (Wed) [3]

A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks

王韋翔

2025-05-26 (Mon) [1]

A Simulation-Guided Paradigm for Logic Synthesis and Verification

程采婕

2025-05-26 (Mon) [2]

Automated Trigger Activation by Repeated Maximal Clique Sampling

曹瀚文

2025-05-26 (Mon) [3]

Circuit Learning: From Decision Trees to Decision Graphs

白琪澤

2025-05-26 (Mon) [4]

Faster AND-OR Path Circuits

蔡皓宇

2025-05-26 (Mon) [5]

ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set

陳祈瑋

2025-05-26 (Mon) [6]

Randomized Transduction for High-Effort Logic Synthesis

張芝岑

2025-05-28 (Wed) [1]

MERO: A Statistical Approach for Hardware Trojan Detection

沈安婕

2025-05-28 (Wed) [2]

Scalable Logic Rewriting Using Don't Cares

張恆祐

2025-05-28 (Wed) [3]

Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach

林奕安

2025-06-02 (Mon) [1]

Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization

廖哲緯

2025-06-02 (Mon) [2]

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis

黃霈紳

2025-06-02 (Mon) [3]

LOOPLock 3.0: A Robust Cyclic Logic Locking Approach

賴琮翰

2025-06-02 (Mon) [4]

Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs

白偉廷

2025-06-02 (Mon) [5]

Area-Driven FPGA Logic Synthesis Using Reinforcement Learning

李昶勳