Announcements
Course Materials
Chapter 1
Representations for Boolean Functions
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1.1 Representations for Boolean Functions
Chapter 2
Two-Level Logic Minimization
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2.1 Exact Minimization
Chapter 3
Multi-Level Logic Minimization
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Chapter 4
Timing Optimization
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Chapter 5
Technology Mapping
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Chapter 6
Synthesis for Finite State Machines
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Chapter 7
Low Power Design
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Chapter 8
Automatic test pattern generation & Logic optimization
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Chapter 9
Hardware Security
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Homework
Tools
SIS
Division Based Multi-level minimizer
Supplementary Materials:
Benchmark
Benchmark
Presentation
2026-05-27 (Wed) [1]
Fast Boolean Matching Based on NPN Classification
黃律瑛
2026-05-27 (Wed) [2]
Delay Optimization Using SOP Balancing
郭紫葳
2026-05-27 (Wed) [3]
LUT-Based Optimization For ASIC Design Flow
鄭凱方
2026-06-01 (Mon) [1]
Rethinking AIG Resynthesis in Parallel
賈俊佑
2026-06-01 (Mon) [2]
DRiLLS: Deep Reinforcement Learning for Logic Synthesis
白淳文
2026-06-01 (Mon) [3]
METRICS 2.0: A Machine-Learning Based Optimization System for IC Design
陳庭竣
2026-06-01 (Mon) [4]
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
傅豐樺
2026-06-01 (Mon) [5]
DeepGate: Learning Neural Representations of Logic Gates
王子銜
2026-06-01 (Mon) [6]
DAG-Aware Synthesis Orchestration
管奕凱
2026-06-01 (Mon) [7]
Scalable Logic Rewriting Using Don't Cares
周明賢
2026-06-03 (Wed) [1]
High-Effort Logic Synthesis Using Randomized Transduction
鄧星宇
2026-06-03 (Wed) [2]
Recurrent Deep Differentiable Logic Gate Networks
謝師誠
2026-06-03 (Wed) [3]
Logic Synthesis for Digital In-Memory Computing
邱珮綸
2026-06-08 (Mon) [1]
Logic Synthesis Optimization Sequence Tuning Using RL-Based LSTM and Graph Isomorphism Network
洪梓翔
2026-06-08 (Mon) [2]
Improved Depth-Aware Circuit Partitioning for Mixed Logic Synthesis
林哲健
2026-06-08 (Mon) [3]
ML-Inspired Logic Synthesis: Improving Multiplier Circuits
鄧同恩
2026-06-08 (Mon) [4]
ExactMap: Enhancing Delay Optimization in Parallel ASIC Technology Mapping
謝心舫
2026-06-08 (Mon) [5]
SAT-Based Logic Optimization and Resynthesis
陳啟綸
2026-06-08 (Mon) [6]
Hardware Trojans Classification for Gate-level Netlists based on Machine Learning
黃守翊