Publication List of Professor Youn-Long Lin

Department of Computer Science, National Tsing Hua University

(Last Updated: March 2016)

MyCitations from Google Scholar http://scholar.google.com/citations?user=jYgzZWIAAAAJ&hl=en

Journal PapersConference PapersBooks & Book ChaptersPatents;  Invited Talks;

Journal Papers

1.          Youn-Long Lin and Daniel D. Gajski, ``LES: A Layout Expert System,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 7, No. 8, pp. 868-876, August 1988.

2.          Youn-Long Lin, Yu-Chin Hsu and Fur-Shing Tsai, ``SILK: A Simulated Evolution Router,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 8, No. 10, pp. 1108-1114, October 1989.

3.          Youn-Long Lin, Yu-Chin Hsu and Fur-Shing Tsai, ``Hybrid Routing,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 2, pp. 151-157, February 1990.

4.          Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin and Yu-Chin Hsu, ``A Fast Transistor-Chaining Algorithm for CMOS Cell Layout,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 7, pp. 781-786, July 1990.

5.          Youn-Long Lin and Yu-Chin Hsu, ``A New Algorithm for Tile Generation,'' INTEGRATION, the VLSI Journal, Vol. 9, No. 3, pp. 259-269, 1990.

6.          Ta-Yung Liu and Youn-Long Lin, ``FLORA: A Data Path Allocator Based on Branch-and-Bound Search,'' INTEGRATION, the VLSI Journal, Vol. 11, No. 1, pp. 43-66, March 1991.

7.          Yu-Chin Hsu, Youn-Long Lin, Han-Chin Hsieh and Tin-Hai Chao, ``Combining Logic Minimization and Folding for PLAs,'' IEEE Transactions on Computers, Vol. 40, No. 6, pp. 706-713, June 1991.

8.          Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin and Yu-Chin Hsu, ``LiB: A CMOS Cell Compiler,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, No. 8, pp. 994-1005, August 1991.

9.          Min-Sian Lin, Horng-Wern Perng, Chi-Yi Hwang and Youn-Long Lin, ``Channel Density Reduction by Routing Over-the-Cell,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 10, No. 8, pp. 1067-1071, August 1991.

10.      Yirng-An Chen, Youn-Long Lin and Long-Wen Chang, ``A Systolic Algorithm for the k-Nearest Neighbors Problem,'' IEEE Transactions on Computers, Vol. 41, No. 1, pp. 103-108, January 1992.

11.      Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin and Yu-Chin Hsu, ``An Efficient Layout Style for 2-Metal CMOS Leaf Cells and Its Automatic Synthesis,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 3, pp. 410-424, March 1993.

12.      Cheng-Tsung Hwang, Yu-Chin Hsu and Youn-Long Lin, ``PLS: A Scheduler for Pipeline Synthesis,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 9, pp. 1279-1286, September 1993.

13.      Yi-Min Jiang, Tsing-Fa Lee, Ting-Ting Hwang and Youn-Long Lin, ``Performance-Driven Interconnection Optimization for Microarchitecture Synthesis,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. 2, pp. 137-149, February 1994.

14.      Tsing-Fa Lee, Chung-Hao Wu, Youn-Long Lin and Daniel D. Gajski, ``A Transformation-Based Method for Loop Folding,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. 4, pp. 439-450, April 1994.

15.      Chung-Haw Allen Wu and Youn-Long Lin, ``High-Level Synthesis -- A Tutorial,'' IEICE Transactions on Information and Systems (Japan), Special Issue on Synthesis and Verification of Hardware Design, (invited), Vol. E78-D, No. 3, pp. 209-218, March 1995.

16.      Yu-Wen Tsay and Youn-Long Lin, ``A Row-Based Cell Placement Method That Utilizes Circuit Structural Properties,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, N0. 3, pp. 393-397, March 1995.

17.      Ching-Dong Chen, Yirng-An Chen, Allen C-H. Wu, and Youn-Long Lin, ``TRACER-fpga: A Router for RAM-Based FPGAs,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, N0. 3, pp. 371-374, March 1995.

18.      Chau-Shen Chen, Yu-Wen Tsay, Ting-Ting Hwang, Allen C-H. Wu, and Youn-Long Lin, ``Combining Technology Mapping and Placement for Delay-Minimization in FPGA Designs,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 9, pp. 1076-1084, September 1995.

19.      Tsung-Yi Wu and Youn-Long Lin, ``Register Minimization Beyond Sharing Among Variables,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 12, pp. 1583-1587, December 1996.

20.      Youn-Long Lin, ``Recent Development in High Level Synthesis,'' ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 2, No. 1, pp. 2-21, January 1997.

21.      Hsiao-Pin Su and Youn-Long Lin, ``A Phase Assignment Method for Virtual Wire Based Hardware Emulation,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No 7, pp. 776-783, July 1997. PDF file

22.      Hsiao-Pin Su, Allen C-H. Wu and Youn-Long Lin, ``A Timing-Driven Soft-Macro Placement and Resynthesis Method in Interaction with Chip Floorplanning,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No 4, pp. 475-483, April 1999. PDF file

23.      Wei-Kai Cheng and Youn-Long Lin, ``Code Generation of Nested Loops for DSP Processors with Heterogeneous Registers and Structural Pipelining,'' ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 3, No 4, pp. 231-256 July 1999. Postscript file

24.      Yi-Chih Chou and Youn-Long Lin, ``Effective Enforcement of Path Delay Constraints in Performance-Driven Placement,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 21, Issue:1, Jan. 2002, Pages: 15-22 PDF file

25.      Kai-Yuan Jan, Chih-Bin Fan, An-Chao Kuo, Wen-Chi Yen, and Youn-Long Lin, ''A Platform-based SOC Design Methodology and Its Application in Image Compression,'' Special Issue on HW-SW Codesign for SoC, International Journal of Embedded Systems, Inderscience Publishers, USA. Vol. 1, Issue 1/2 , pp. 23-32, 2005.

26.      Tai-Yi Huang, Chung-Ta King, Yin-Tsung Hwang, and Youn-Long Lin, "The Embedded Software Consortium of Taiwan," ACM Transactions on Embedded Computing Systems (TECS) Special Issue on Embedded Systems Education, Volume 4, Issue 3, pp. 612-632, August  2005.

27.      Yuan-Chun Lin and Youn-Long Lin, "A Two-Result-Per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume: 17, Number: 6, June 2009, Pages: 838-843.

28.      Jian-Wen Chen and Youn-Long Lin, "A High-performance Hardwired CABAC Decoder for Ultra-high Resolution Video," IEEE Transactions on Consumer Electronics, Volume 55, Issue 3, pp. 1614-1622, August 2009.

29.      Huan-Kai Perng and Youn-Long Lin, "Optimal Warning-Zone-Length Assignment Algorithm for Real-time, Multiple-QoS On-Chip Bus Arbitration," ACM Transactions on Embedded Computing Systems (TECS), Volume 9, Issue 4, Article 35, March 2010.

30.      Chao-Yang Kao, Cheng-Long Wu and Youn-Long Lin, "A High Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 18, Number 4, April 2010, Pages: 662-666.

31.      Chao-Yang Kao and Youn-Long Lin, "A  Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC, " IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 18, No 6, June 2010, Pages: 866-874.

32.      Jian-Wen Chen, Li-Cian Wu, Po-Seng Liu and Youn-Long Lin, "A High-throughput Fully Hardwired CABAC Encoder for QFHD H.264/AVC Main Profile Video," IEEE Transactions on Consumer Electronics, November 2010, Pages: 2529-2536.

33.      Huang-Chih Kuo, Li-Cian Wu, Hao-Ting Huang, Sheng-Tsung Hsu, and Youn-Long Lin, "A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 19, No 6, June 2011, Pages: 925-938.

34.      Chia-Ming Hung and Youn-Long Lin "3D IC Implementation of Multiple Applications Emphasizing Manufacture Reuse,"  IET Computers & Digital Techniques, Volume 5, Issue 3, May 2011, Pages: 179-185.

35.      Huang-Chih Kuo and Youn-Long Lin, "A Hybrid Algorithm for Effective Lossless Compression of  Video Display Frames," IEEE Transactions on Multimedia, Volume 14, Number 3, June 2012, Pages: 500-509.

36.      Wen -Tsuen Chen, Youn-Long Lin, Chen-Yi Lee, Jeng-Long Chiang, Meng-Fan Chang, Shih-Chieh Chang, "Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan," IEEE Access, Vol. 1, No. 1, pp. 123-130, 2013

37.      Hock Chen, Youn-Long Lin and Mango C-T. Chao, "Power-up Sequence Control for MTCMOS Designs," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Volume 21, No 3, March 2013, Pages: 413-423.

38.      Huang-Chih Kuo and Youn-Long Lin, "VLSI Architecture Design for H.264/AVC Intra-Frame Encoding,"  IPSJ Transactions on System LSI Design Methodology (TSLDM) Vol. 6 (2013) pp. 76-93 (Invited).

 

Conference Papers

1.          Daniel D. Gajski, Youn-Long Lin and Chidchanok Lursinsap, ``Silicon Cell Compilers,'' NATO Advanced Study Institute on Logic Synthesis and Silicon Compilation for VLSI Design, SSGRR - L'Aquila, Italy, July 1986.

2.          Youn-Long Lin, Daniel D. Gajski and Haruyuki Tago, ``A Flexible-Cell Approach to Module Generation,'' Custom Integrated Circuits Conference(CICC), Portland, Oregon, U.S.A., May 1987.

3.          Youn-Long Lin and Daniel D. Gajski, ``LES: A Layout Expert System,'' 24th ACM/IEEE Design Automation Conference(DAC), Miami Beach, Florida, U.S.A., June 1987.

4.          Youn-Long Lin, Yu-Chin Hsu and Fur-Shin Tsai, ``Detailed Routing Based on Simulated Evolution,'' International Conference on Computer-Aided Design(ICCAD), Santa Clara, California, U.S.A., pp. 38-41, November 1988.

5.          Yirng-An Chen, Youn-Long Lin and Yu-Chin Hsu, ``A New Global Router for ASIC Design Based on Simulated Evolution,'' International Symposium on VLSI Technologies, Systems and Applications, Taipei, Taiwan, pp. 261-265, May 1989.

6.          Chu-Yi Huang, Yin-Shen Chen, Youn-Long Lin and Yu-Chin Hsu, ``Two New Algorithms for Data-Path Allocation,'' International Symposium on VLSI Technologies, Systems and Applications, Taipei, Taiwan, pp. 129-133, May 1989.

7.          Jiahn-Hurng Lee, Yu-Chin Hsu and Youn-Long Lin, ``LIP: A Data-Path Scheduler Using Linear Integer Programming,'' International Symposium on VLSI Technologies, Systems and Applications, Taipei, Taiwan, pp.247-251, May 1989.

8.          Youn-Long Lin, Yu-Chin Hsu, Chi-Yi Hwang and Yung-Ching Hsieh, ``A Graph-Theoretical Approach to Transistor Placement in a CMOS Cell Layout,'' 32nd Midwest Symposium on Circuits and Systems, Urbana, Illinois, August 1989.

9.          Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin and Yu-Chin Hsu, ``An Optimal Transistor-Chaining Algorithm for CMOS Cell Layout,'' International Conference on Computer-Aided Design(ICCAD), Santa Clara, California, U.S.A., pp. 344-347, November 1989.

10.      Jiahn-Hurng Lee, Yu-Chin Hsu and Youn-Long Lin , ``A New Linear Integer Programming Scheduler for Data Path Synthesis,'' International Conference on Computer-Aided Design(ICCAD), Santa Clara, California, U.S.A., pp. 20-23, November 1989.

11.      Youn-Long Lin, Yu-Chin Hsu and Fur-Shing Tsai, ``Routing Using a Pyramid Data Structure,'' International Conference on Computer-Aided Design(ICCAD), Santa Clara, California, U.S.A., pp. 436-439, November 1989.

12.      Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin and Yu-Chin Hsu, ``LiB: A Cell Layout Generator,'' 27th ACM/IEEE Design Automation Conference(DAC), Orlando, Florida, June 1990, pp. 474-479.

13.      Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin and Yu-Chin Hsu, ``Data Path Allocation Based on Bipartite Weighted Matching,'' 27th ACM/IEEE Design Automation Conference(DAC), Orlando, Florida, June 1990, pp. 499-504.

14.      Cheng-Tsung Hwang, Yu-Chin Hsu and Youn-Long Lin, ``Optimum and Heuristic Data Path Scheduling under Resource Constraints,'' 27th ACM/IEEE Design Automation Conference(DAC), Orlando, Florida, June 1990, pp. 65-70.

15.      Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin and Yu-Chin Hsu, ``An Efficient Layout Style for 2-Metal CMOS Leaf Cells,'' 2nd Physical Design Automation Workshop, Pennsylvania, May 1991.

16.      Min-Sian Lin, Horng-Wern Perng, Chi-Yi Hwang and Youn-Long Lin, ``Channel Density Reduction by Routing Over the Cells,'' 28th ACM/IEEE Design Automation Conference(DAC), San Francisco, California, June 1991, pp. 120-125.

17.      Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin and Yu-Chin Hsu, ``An Efficient Layout Style for 2-Metal CMOS Leaf Cells and Their Automatic Generation,'' 28th ACM/IEEE Design Automation Conference(DAC), San Francisco, California, June 1991, pp. 481-486.

18.      Cheng-Tsung Hwang, Yu-Chin Hsu and Youn-Long Lin, ``Scheduling for Functional Pipelining and Loop Winding,'' 28th ACM/IEEE Design Automation Conference(DAC), San Francisco, California, June 1991, pp. 764-769.

19.      Mu-Hoarn Tsai, Ting-Ting Hwang and Youn-Long Lin, ``Technology Mapping for Field Programmable Gate Arrays Using Binary Decision Diagram,'' Proceedings of the Synthesis and Simulation Meeting and International Interchange (SASIMI '92), Kobe, Japan, April 1992, pp. 84-92.

20.      Tsing-Fa Lee, Allen C-H. Wu and Youn-Long Lin, ``A New Algorithm for Pipelining Loop Execution,'' Proceedings of the Synthesis and Simulation Meeting and International Interchange (SASIMI '92), Kobe, Japan, April 1992, pp. 198-207.

21.      Wei-Po Lee and Youn-Long Lin, ``Logic Gate Sizing for Cell-Based Designs,'' International Symposium on Logic Synthesis and Microprocessor Architecture, Iizuka, Fukuoka, Japan, July 1992, pp. 115-123.

22.      Yi-Min Jiang, Tsing-Fa Lee, Ting-Ting Hwang and Youn-Long Lin, ``Performance Driven Interconnection Optimization for Microarchitecture Synthesis,'' European Design Automation Conference (EURO-DAC), Hamburg, Germany, September 1992, pp. 118-123.

23.      Tsing-Fa Lee, Allen C-H. Wu, Daniel D. Gajski and Youn-Long Lin, ``An Effective Methodology for Functional Pipelining,'' International Conference on Computer-Aided Design(ICCAD), Santa Clara, California, U.S.A., November 1992.

24.      Yu-Wen Tsay, Chung-Hao Wu and Youn-Long Lin, ``A Cell Placement Procedure That Utilizes Circuit Structural Properties,'' EDAC-EUROASIC, Paris, France, February 1993, pp. 189-193.

25.      Yu-Wen Tsay, Perng-Chuan Hwang and Youn-Long Lin, ``Rectilinear Steiner Tree Generation Under a Distributed-RC Delay Model,'' Proceedings of the Synthesis and Simulation Meeting and International Interchange (SASIMI '93), Nara, Japan, October 20-22, 1993, pp. 245-254.

26.      Wei-Jeng Chen, Tsing-Fa Lee, Allen C-H. Wu and Youn-Long Lin, ``On the Relationship between Sequential Logic Retiming and Loop Folding,'' Proceedings of the Synthesis and Simulation Meeting and International Interchange (SASIMI '93), Nara, Japan, October 20-22, 1993, pp. 384-393.

27.      Chau-Shen Chen, Yu-Wen Tsay, Ting-Ting Hwang, Allen C-H. Wu, and Youn-Long Lin, ``Combining Technology Mapping and Placement for Standard Cell Designs,'' Proceedings of the Synthesis and Simulation Meeting and International Interchange (SASIMI '93), Nara, Japan, October 20-22, 1993, pp. 394-403.

28.      Chau-Shen Chen, Yu-Wen Tsay, Ting-Ting Hwang, Allen C-H. Wu, and Youn-Long Lin, ``Combining Technology Mapping and Placement for High-Performance FPGA Designs,'' International Conference on Computer-Aided Design(ICCAD), Santa Clara, California, U.S.A., November 1993.

29.      Tsung-Yi Wu, Tzu-Chie Tien, Chung-Hao Wu and Youn-Long Lin, ``A Synthesis Method for Mixed Synchronous/Asynchronous Behavior,'' EDAC-ETC-EUROASIC, Paris, France, February 1994.

30.      Wei-Kai Cheng and Youn-Long Lin, ``Code Generation for a DSP Processor,'' 7th International Symposium on High-Level Synthesis, Niagara-on-the-Lake, Ontario, Canada, May 18-20, 1994.

31.      Kuo-Hwa Wang, Wen-Shin Wang, Ting-Ting Hwang, Chung-Hao Wu and Youn-Long Lin, ``State Assignment for Area and Power Minimization,'' International Conference on Computer Design , Cambridge, Mass., U.S.A., October 1994.

32.      Tsung-Yi Wu and Youn-Long Lin, ``A New Register Minimization Method for the Synthesis of Control-Dominated Circuits,'' Asia-Pacific Conference on Hardware Description Language (APCHDL), Toyohashi, Japan, October 1994.

33.      Wei-Kai Cheng and Youn-Long Lin, ``A Transformation-Based Method for Storage Optimization,'' ACM/IEEE 32nd Design Automation Conference , San Francisco, California, U.S.A., June 1995.

34.      Tsung-Yi Wu and Youn-Long Lin, ``Register Minimization beyong Sharing among Variables,'' ACM/IEEE 32nd Design Automation Conference , San Francisco, California, U.S.A., June 1995.

35.      Tsung-Yi Wu and Youn-Long Lin, ``Storage Optimization by Replacing some Flip-Flops with Latches,'' European Design Automation Conference (EURO-DAC), Geneva, Switzerland, September, 1996.

36.      Yu-Wen Tsay, Hsiao-Pin Su, and Youn-Long Lin, ``An Improved Objective for Cell Placement,'' Asia and South-Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, January 1997.

37.      Yu-Wen Tsay, Wen-Jone Feng, Allen C-H. Wu, and Youn-Long Lin, ``Preserving HLS Hierarchy in Cell-Based Design,'' International Symposium on Physical Design (ISPD), Napa Valley, California, U.S.A., April 1997.

38.      Hsiao-Pin Su, Allen C-H. Wu, and Youn-Long Lin, ``Performance-Driven Soft-Macro Clustering and Placement by Preserving HDL Design Hierarchy,'' International Symposium on Physical Design (ISPD), Monterey, California, U.S.A., April 1998.

39.      Yih-Chih Chou and Youn-Long Lin, ''A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization,'' International Conference on Computer-Aided Design(ICCAD), San Jose, California, U.S.A., November 1998. Postscript file PowerPoint file

40.      Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, and Youn-Long Lin, ''Integrating Logic Retiming and Register Placement,'' International Conference on Computer-Aided Design(ICCAD), San Jose, California, U.S.A., November 1998. Postscript file PowerPoint file

41.      Wei-Kai Cheng and Youn-Long Lin, ``DSP Addressing Optimization for Loop Execution on the Auto-Increment/Decrement Architecture,'' International Symposium on System Synthesis(ISSS), Hsin-Chu, Taiwan, December 1998. Postscript file PowerPoint file

42.      Yun-Yin Lian and Youn-Long Lin, ``Layout-Based Logic Decomposition for Timing Optimization,'' Asia and South Pacific Design Automation Conference(ASP-DAC), Hong Kong, China, January 1999. Postscript file PowerPoint file

43.      Hsiao-Pin Hsu, Allen C-H. Wu and Youn-Long Lin, ``A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning,'' 36th ACM/IEEE Design Automation Conference(DAC), New Orleans, LA, U.S.A., June 1999. Postscript file PowerPoint file

44.      Tzu-Chieh Tien and Youn-Long Lin, ``Performance-optimal clustering with retiming for sequential circuits,'' Asia and South Pacific Design Automation Conference(ASP-DAC), (Best Paper Award Candidate). Yokohama, Japan, January 2000. Postscript file PowerPoint file

45.      Hon-Kai Chang and Youn-Long Lin, ``Array allocation taking into account SDRAM characteristics,'' Asia and South Pacific Design Automation Conference(ASP-DAC), Yokohama, Japan, January 2000. Word file PowerPoint file

46.      Michael C J Lin and Youn-Long Lin, ``A VLSI Implementation of the Blowfish Encryption/Decryption Algorithm,'' Asia and South Pacific Design Automation Conference(ASP-DAC), Yokohama, Japan, January 2000. (The Outstanding Design Award, Univ. LSI Design Contest). Word file PowerPoint file

47.      Yih-Cih Chou and Youn-Long Lin, ``A 3-Step Approach for Performance-Driven Whole Chip Routing,'' Asia and South Pacific Design Automation Conference(ASP-DAC), Yokohama, Japan, January 2001. PDF file PowerPoint file

48.      Yih-Cih Chou and Youn-Long Lin, ``A Performance-driven Standard Cell Placer based on a Modified Force-directed Algorithm,'' International Symposium on Physical Design(ISPD), Sonoma County, CA, USA, April 2001. PDF file PowerPoint file

49.      Hung-Ping Wen and Youn-Long Lin, ``Concurrent-Simulation-Based Remote IP Evaluation over the Internet for System-On-Chip Design,'' International Symposium on System Synthesis(ISSS), Montreal, Canada, October 2001. PDF file PowerPoint file

50.      Chih-Chun Chang and Youn-Long Lin, ``A Dual Mode (5, 3)/(9,7) FDWT/IDWT Hardware Accelerator IP,'' 15th VLSI Design/CAD Symposium, Kenting, Taiwan, August 2004. PDF file

51.      Tien-Wei Hsieh and Youn-Long Lin, ``A Low Power and High Performance EBCOT Architecture of JPEG2000 Encoding,'' 15th VLSI Design/CAD Symposium, Kenting, Taiwan, August 2004. PDF file

52.      Tien-Wei Hsieh and Youn-Long Lin, ``A Hardware Accelerator IP for EBCOT Tier-1 Coding in JPEG2000 Standard,'' IEEE 2nd Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Stockholm, Sweden, September 2004. PDF file PPT file

53.      Chih-Chun Chang and Youn-Long Lin, ``A Parameterized On-Chip-Bus-Compliant FDWT/IDWT Accelerator IP Generator,'' Twelveth Synthesis And System Integration of Mixed Information technologies (SASIMI), Kanazawa, Japan, October 2004.  PDF file

54.      Chao-Yung Kao and Youn-Long Lin, ``An AMBA-Compliant Motion Estimator For H.264 Advanced Video Coding, '' IEEE International SOC Conference (ISOCC), Seoul, Korea, October 2004. PDF file

55.      Youn-Long Lin, ''How Do They Manage Designing Complex SOC? -- One-page Introduction to the Special Session, '' IEEE/ACM Design, Automation and Test of Europe (DATE), Munich, Germany, March 2005. PDF file

56.      Chien-Liang Chen, Jiing-Yuan Lin and Youn-Long Lin, ''Integration, Verification and Layout of a Complex Multimedia SOC, '' IEEE/ACM Design, Automation and Test of Europe (DATE), Munich, Germany, March 2005. PDF file

57.      Wen-Chi Yen, An-Chi Chen, Po-Sheng Liu and Youn-Long Lin, '' A Hardware/Software-Concurrent JPEG2000 Encoder, '' IEEE VLSI-TSA Design, Automation and Test, (vlsi-dat), hSIN-cHU, tAIWAN, aPRIL 2005.

58.      Jian-Wen Chen, Cheng-Ru Chang and Youn-Long Lin, '' A Hardware Accelerator for Context-Based Adaptive Binary Arithmetic Decoding in H.264/AVC, '' IEEE INTERNATIONAL sYMPOSIUM ON cIRCUITS AND sYSTEMS (iscas), kOBE, jAPAN, mAY 2005.

59.      Shen-Yu Shih, Cheng-Ru Chang and Youn-Long Lin, ''AN AMBA-COMPLIANT DEBLOCKING FILTER IP FOR H.264/AVC , '' IEEE INTERNATIONAL sYMPOSIUM ON cIRCUITS AND sYSTEMS (iscas), kOBE, jAPAN, mAY 2005.

60.      Huang-Chun Tseng, Cheng-Ru Chang and Youn-Long Lin, "A Motion Compensator with Parallel Memory for H.264 Advance Video Coding, " 16th VLSI Design/CAD Symposium, Hualien, Taiwan, August 2005.

61.      Huang-Chun Tseng, Cheng-Ru Chang and Youn-Long Lin, "A Hardware Accelerator for H.264/AVC Motion Compensation, " 2005 IEEE Workshop on Signal Processing Systems (SiPS 2005), Athens, Greece, November 2005.

62.      Shen-Yu Shih, Cheng-Ru Chang and Youn-Long Lin, "A Near Optimal Deblocking Filter for H.264 Advanced Video Coding," IEEE/ACM Asia-South Pacific Design Automation Conference, Yokohama, Japan, January 2006.

63.      Jian-Wen Chen, Chao-Yung Kao and Youn-Long Lin, "Introduction to H.264/AVC and the Special Session," IEEE/ACM Asia-South Pacific Design Automation Conference, Yokohama, Japan, January 2006.

64.      Cheng-Ru Chang, Jian-Wen Chen, Tzu-Jen Lo, Chun-Lin Chiu, Yen-Hong Chang, Huan-Chun Tzeng, Shen-Yu Shih, Yu-Chen Kao, Chao-Yang Kao, Youn-Long Lin, "An H.264/AVC Main Profile Hardwired Decoder," 2006 Picture Coding Symposium (PCS), Beijing, China, April 24-26, 2006.

65.      Chao-Yang Kao, Huang-Chih Kuo and Youn-Long Lin, "High Performance Fractional Motion Estimation and Mode Decision for H.264/AVC,"  IEEE International Conference on Multimedia & Expo (ICME), Toronto, Canada, July 9-12, 2006.

66.      Yuan-Chun Lin, Ping Chao, Wei-Cheng Hung, Huan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Kai-Yuan Jan, "A Pure Hardwired H.264/AVC Video Decoder on an SOC Platform," International SOC Conference (ISOCC), Seoul, Korea, October 26-27, 2006. (Student Design Contest)

67.      Yu-Chien Kao, Huang-Chi Guo, Yin-Tzu Lin, Chia-Wen Hou, Yi-Hsien Li, Hao-Tin Huang, and Youn-Long Lin, "A High-Performance VLSI Architecture for  Intra Prediction and Mode Decision in  H.264/AVC Video Encoding," IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), Singapore, December 2006.

68.      Huan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, Ping Chao, Wei-Cheng Hung, Kai-Yuan Jan, "A Highly Integrated 8 mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16 MHz SoC Platform," IEEE/ACM 12th Asia and South-Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 23-26, 2007. (University LSI Design Contest)

69.      Po-Sheng Liu, Jian-Wen Chen, Youn-Long Lin, A Hardwired Context-Based Adaptive Binary Arithmetic Encoder for H.264 Advanced Video Coding, IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsin-Chu, Taiwan, April 25-27, 2007.

70.      Jian-Wen Chen and Youn-Long Lin, A High-Performance Hardwired CABAC Decoder, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Honolulu, Hawaii, USA, April 15-20, 2007.

71.      Ping Chao and Youn-Long Lin, "A Motion Compensation System with a High Efficiency Reference Frame Pre-Fetch Scheme for QFHD H.264/AVC Decoder," IEEE International Conference on Circuits and Systems (ISCAS),  Seattle, WA, USA, May 2008.

72.      Ping Chao and Youn-Long Lin, "Reference Frame Access Optimization for Ultra High Resolution H.264/AVC Decoding," IEEE International Conference on Multimedia & Expo (ICME), Hannover, Germany, June 23-26, 2008.

73.      Cheng-Long Wu, Chao-Yang Kao and Youn-Long Lin, "A High Performance THree-Engine Architecture for H.264/AVC Fractional Motion Estimation," IEEE International Conference on Multimedia & Expo (ICME), Hannover, Germany, June 23-26, 2008.

74.      Chao-Yang Kao and Youn-Long Lin, "A High-Performance and Memory-Efficient Architecture for H.264/AVC Motion Estimation," IEEE International Conference on Multimedia & Expo (ICME), Hannover, Germany, June 23-26, 2008.

75.      Huang-Chih Kuo and Youn-Long Lin, "An H.264/AVC Full-Mode Intra-Frame Encoder for 1080HD Video," IEEE International Conference on Multimedia & Expo (ICME), Hannover, Germany, June 23-26, 2008.

76.      Kai-Yuan Jan and Youn-Long Lin, "An Electronics System-Level Design Methodology with a Motion-JPEG Encoder Case Study," 16th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2008, October 13-15, 2008, Rhodes Island, Greece.

77.      Lih-Cian Wu and Youn-Long Lin, "A High Throughput CABAC Encoder for Ultra High Resolution Video," IEEE International Conference on Circuits and Systems (ISCAS), Taipei, Taiwan, May 2009.

78.      Hui-Ting Yang, Jian-Wen Chen, Huang-Chih Kuo and Youn-Long Lin, "An Effective Dictionary-based Display Frame Compressor," IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Grenoble, France, October 15-16, 2009

79.      Huang-Chih Kuo, Jian-Wen Chen and Youn-Long Lin, "A High-Performance Low-Power H.264/AVC Video Decoder Accelerator for Embedded Systems, " IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Grenoble, France, October 15-16, 2009

80.      Kai-Hsiang Chang and Youn-Long Lin, "A Very High Throughput Fully Hardwired CABAC Decoder," IEEE International Symposium on Intelligent Signal Processing and Communication (ISPACS), December 7-9, 2009, Kanazawa, Japan.

81.      Kai-Yuan Jan, Charles H.-P. Wen and Youn-Long Lin, "A Learning-based Test-selection Strategy for Video Encoders, "10th IEEE International Workshop on Microprocessor Test and Verification (MTV '09)," Austin, Texas, December 7-9, 2009

82.      Huang-Chih Kuo and Youn-Long Lin, "Applications of Low Power Technologies on Video Codec VLSI Designs," IEEE International Conference on Green Circuits and Systems (ICGCS), June 2010, Shanghai, China.

83.      Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, and Youn-Long Lin, "A Customized Design of DRAM Controller for On-Chip 3D DRAM Stacking," IEEE Custom Integrated Circuits Conference (CICC), September 2010, San Jose, CA, USA.

84.      Ping Chao and Youn-Long Lin, "An Elastic Software Cache with Fast Prefetching for Motion Compensation in Video Decoding,"  IEEE/ACM The International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), October 2010, Scottsdale, AZ, USA.

85.      Ho Huang and Youn-Long Lin, "Scheduling for Synthesizing Portable System with Energy Harvesting and Storage," Annual Conference of  Asia Pacific Signal and Information Processing Association (APSIPA) , December 2010, Singapore.

86.      Huang-Chih Kuo and Youn-Long Lin, "A simple and effective lossless compression algorithm for video display frames," IEEE International Conference on Multimedia & Expo (ICME), July 2011, Barcelona, Spain.

 

Books & Book Chapters

1.    Daniel D. Gajski, Nikil D. Dutt, Allen C-H. Wu and Youn-Long Lin, ``High-Level Synthesis -- Introduction to Chip and System Design,'' Kluwer Academic Publishers CO., 1992.

2.    Youn-Long Lin, editor, "Essential Issues in SOC Design," Springer-Verlag, 2006.

3.    Daniel D. Gajski and Youn-Long Lin, ``Module Generation and Silicon Compilation,'' in Physical Design Automation of VLSI Systems, Bryan T. Preas and Michael J. Lorenzetti, editors, Benjamin/Cummings, 1988.

4.    Youn-Long Lin, Chidchanok Lursinsap and Daniel D. Gajski, ``Silicon Cell Compiler,'' in Advances in Computer-Aided Engineering Design, Vol. 2, Ibrahim. N. Hajj, editor, JAI Press Ltd., 1990.

5.    Yu-Chin Hsu and Youn-Long Lin, ``High Level Synthesis in the Theda System,'' in High Level Synthesis, Raul Camposano and Wayne Wolf, editors, Kluwer Academic Publishers Co., 1991.

6.    Wei-Po Lee and Youn-Long Lin, ``Gate Sizing for Cell-Based Designs,'' in Logic Synthesis and Optimization, Tsutomu Sasao, editor, pp. 341-359, Kluwer Academic Publishers Co., 1992.

7.    Youn-Long Lin, editor, "Essential Issues in System-On-a-Chip Design, "Springer-Verlag, 2006.

8.    Youn-Long Lin, "Essential Issues in System-On-a-Chip Design, " in "Essential Issues in SOC Design," Youn-Long Lin Editor, Springer-Verlag, 2006.

9.    Jing-Yuan Lin, Chien-Liang Chen and Youn-Long Lin, "A Digital Still Camera Controller SOC," in "Essential Issues in SOC Design," Youn-Long Lin Editor, Springer-Verlag, 2006.

10. Huan-Kai Peng,  Chun-Hsin Lee,  Jian-Wen Chen,  Tzu-Jen Lo,  Yung-Hung Chang, Sheng-Tsung Hsu,  Yuan-Chun Lin,  Ping Chao,  Wei-Cheng Hung,  Kai-Yuan Jan, Youn-Long Lin, Development of an H.264/AVC Main Profile Video Decoder Prototype using a Platform-Based SOC Design Methodology, " Handbook of Mobile Broadcasting: DVB-H, DMB, ISDB-T and MediaFLO, Editor-in-Chiefs: Borko Furht and Syed Ahson. 2008

11. Youn-Long Lin, Chao-Yang Kao, Huang-Chih Kuo and Jian-Wen Chen, "VLSI Design for H.264/AVC Video Coding -- From Specification to Chip," Springer, 2010.

12. Youn-Long Lin, Chong-Min Kyung, Hiroto Yasuura, Yongpan Liu, Editors, "Smart Sensor Systems," Springer, 2015.

13. Chong-Min Kyung, Hiroto Yasuura, Yongpan Liu, Youn-Long Lin, Editors, "Smart Sensor Systems eHeath and Environment," Springer, 2016.

Patents

1. Youn-Long Lin and Hui-Ting Yang, "Compression method for display frames of QFHD (quad full high definition) resolution and system thereof," US Patent (Patent # 8,213,520), July 3, 2012.

2. Shi-Hao Chen and Youn-Long Lin, "Power booting sequence control system and control method thereof," Us Patent (Patent # 8,539,261), September 17, 2013.

3. Youn-Long Lin, "Apparatus of Automatic Vehicle Suspension Systems using Real-Time Road Contour," US Patent (Patent #8,930,074), January 5, 2015.

4. Youn-Long Lin, DEVICE OF BUILDING REAL-TIME ROAD CONTOUR FOR SUSPENSION CONTROL SYSTEM, Taiwan Paten (Patent# 102130137), November 11, 2015

5.  

 

Invited Presentations

1.      Ming-Fon Liou and Youn-Long Lin, ``Verifying Cache Coherency Protocol in a Multiprocessor System,'' 1996 Asia-Pacific Conference on Hardware Description Languages (APCHDL'96), Bangalore, India, January 1996. (Invited).

2.      Youn-Long Lin, ``Computing Brokerage and Its Applications in VLSI Design,'' Asia and South-Pacific Design Automation Conference (ASP-DAC'97), Chiba, Japan, January 1997. (Invited). PowerPoint file

3.      Youn-Long Lin, ``,'' Asia and South-Pacific Design Automation Conference (ASP-DAC'99), Hong Kong, China, January 1999. (Panel Discussion). PowerPoint file

4.      Youn-Long Lin, ``High Level Synthesis of VLSIs,'' 10th VLSI/CAD Symposium, Don-Pu, Nan-Tou, Taiwan, August 1999. (Invited). One-page Abstract, Word file PowerPoint file

5.      Youn-Long Lin, ``IP -- A Rising Star in the IC Industry,'' Executive Panel, Electronic Design Automation & Test EXPO (EDA&T), Hsin-Chu, Taiwan, October 1999. PowerPoint file

6.      Youn-Long Lin, ``Industry-Academic Cooperation," Asia and South-Pacific Design Automation Conference (ASP-DAC-2000), Yokohama, Japan, January 2000. (Panel Discussion). PowerPoint file

7.      Youn-Long Lin, ``IC Design," Taipei Foundation of Finance, February 21, 2000, PowerPoint file

8.      Youn-Long Lin, ``Digital IP Authoring," Taiwan Silicon IP Consosium, September 2000, PowerPoint file

9.      Yi-Chih Chou and Youn-Long Lin, ``Performance-Driven Placement of Multi-Million-Gate Circuits,'' ASICON 2001, October 2001, Shanghai, China.

10.  Youn-Long Lin, ''SOC Design Foundry,'' China IC Society Annual Meeting, April 2002, Han-Zhou, China.

11.  Juinn-Dar Huang, Jin-Yuan Lin and and Youn-Long Lin, ''SOC Design Methodology and Case Study,'' VLSI/CAD Symposium, August 2002, Tai-Tung, Taiwan.

12.  Youn-Long Lin, ''On Academic Excellence,'' VLSI/CAD Symposium, August 2003, Hua-Lien, Taiwan.

13.  Youn-Long Lin ''Business Issues about IP and SOC Design,'' Japan-Taiwan Symposium on SOC Design, October 2003, Tokyo, Japan.

14.  Youn-Long Lin, ''My Humble Opinion on EDA Research,'' Taiwan EDA Forum Quarterly Meeting, December 2003, Taiepi.

15.  Youn-Long Lin, ''Writing EDA Papers,'' Taiwan EDA Forum Quarterly Meeting, March 2004, Taiepi.

16.  Youn-Long Lin, ''SOC Design: Academic Research, Governmental Initiatives and Industrial Adventure,'' April 2004, IC Design Education Center, KAIST, Daejong, Korea.

17.  Manchi Lan and Youn-Long Lin, ``Ten-Year of Experience in Promoting VLSI Design Education in a Grand Scale,'' International Workshop on Collaboration in Embedded Systems and SOC, April, 2004, Seoul, Korea.

18.  Youn-Long Lin, ''Concurrent Hardware-Software JPEG2000,'' Nakamura Lab, Kyoto University, Japan, October 16, 2004.

19.  Youn-Long Lin, "CEO Professor," Addressing a group of young professors, Yun-Lin, Taiwan, July 2005.

20.  Youn-Long Lin, "Quantitative Presentation of Information," Addressing an EDA summer camp, Hsin-Chu, Taiwan, July 2005.

21.  Youn-Long Lin, "SOC Design Foundry," International Forum on Application-Specific Multi-processor SOC (MPSOC), Bordeaux, France, July 2005.

22.  Youn-Long Lin, "SOC Design Foundry, " 5th Emerging Information Technology Conference (EITC2005), Taipei, Taiwan, August, 2005.

23.  Youn-Long Lin, "A Case of SOC Implementation," SOC Workshop, Kyoto University, Kyoto, Japan, September 2005.

24.  Youn-Long Lin, "SOC Design Foundry and a Case of Complex Multimedia SOC," International SOC Conference (ISOCC2005), Seoul, Korea, October 2005.

25.  Youn-Long Lin, "Development of a Hardwired H.264 Main Profile Decoder, " Embedded System Center, Seoul National University, Seoul, Korea, October 2005.

26.  Youn-Long Lin, "Introduction to Video Coding and Development of a Hardwired H.264/AVC Main Profile Decoder," Part I of a Full-Day Tutorial on "Four New Ways to Design a High Definition Video CODEC," IEEE/ACM DATE Conference, Munich, Germany, March 6-10, 2006.

27.  Youn-Long Lin, "Tutorial on Video Coding with Emphasis on H.264/AVC," A 3-hour Tutorial, Taiwan SOC Consortium, STC, ITRI, Hsin-Chu, Taiwan, March 30, 2006.

28.  Youn-Long Lin, "Development of an H.264/AVC Decoder Prototype on a Multimedia SOC Platform," Distinguished Lecture Series, Center for Embedded Computer Systems, University of California, Irvine, July 11, 2006.

29.  Youn-Long Lin, "My Experience in Writing EDA Papers, " Graduate Student Forum, 17th VLSI Design/CAD Symposium, August 2006, Hua-Lien, Taiwan

30.  Youn-Long Lin, "An H.264/AVC Main Profile Video Codec Accelerator in a MpSOC Platform," 6th International Forum on Application-Specific Multi-processor SOC(MPSOC), August 14-18, 2006, Colorado, USA.

31.  Youn-Long Lin, "Tutorial on Video Coding with Emphasis on H.264/AVC," International SOC Conference(ISOCC), Seoul, Korea, October 26-27, 2006.

32.  Youn-Long Lin, "(1) Tutorial on H.264 Advanced Video Coding; (2) Development of a Hardwired H.264/AVC Main Profile Decoder Prototype; (3) SOC Design Foundry; (4) SOC Implementation Challenges and Case Studies; (5) My Experience in Writing EDA Papers; (6) Research Q&A," Guest Lectures in Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan, November 20-21, 2006.

33.  Youn-Long Lin, "Development of an H.264/AVC Decoder Prototype on a Multimedia SOC Platform," National Chang Hua University, November 24, 2006.

34.  Youn-Long Lin, "My Experience in Writing EDA Papes," National Chiao-Tung University, March 14, 2007

35.  Youn-Long Lin, "IC Design Value Chain," Fu Jen University, Taipei, May 26, 2007

36.  Youn-Long Lin, "On Writing EDA Papers," 2007 EDA Workshop, Sun-Moon-Lake, July 12, 2007.

37.  Youn-Long Lin, "Design Challenge of a Super-HDTV Decoder," 7th International Forum on Application-Specific Multi-processor SOC(MPSOC), Awaji Island, Japan, June 25-29, 2007

38.  Youn-Long Lin, "(1) UDSM SOC Design Challenges and SOC Design Foundry Update; (2) A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Video Decoder; (3) A Motion Compensation System with High Efficiency Refrence-Frame Prefetch Scheme for QFHD H.264/AVC Video Decoder; (4) Effective Presentation of Quantative Information (5) Research Q&A," Guest Lectures in Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan, November 26-27, 2007.

39.  Youn-Long Lin, "Some Experience of and Some Observation by an Engineer," Graduate Institute of Microelectronics, National Taiwan University, December 31, 2007.

40.  Youn-Long Lin, Panel Discussion in "The Tears and Joy of Sowing and Reaping Complex SoC's," IEEE/ACM Asia-South Pacific Design Automation Conference (ASP-DAC), January 21-24, 2008, Seoul, Korea. (Moderator: Ing-Jer Huang (Nat'l Sun Yat-Sen Univ., Taiwan), Panelists: Youn-Long Lin (Nat'l Tsing Hua Univ./Global UniChip, Taiwan), Hoonmo Yang (Core Logic, Republic of Korea), Toshihiro Hattori (Renesas, Japan), Ahmed Jarraya (CEA-LETI, MINATEC, France), Xu Chen (Peking Univ., China)).

41.  Youn-Long Lin, "Some Experience of and Some Observation by an Engineer," Department of Electrical Engineering, National Taiwan University, February 25, 2008.

42.  Youn-Long Lin, "Memory Access Analysis and Optimization for Ultra High Definition Video Decoding," 8th International Forum on Application-Specific Multi-processor SOC(MPSOC), Valkenburg, a.d. Geul (Aachen/Maastritch), the Netherlands, June 23-27, 2008

43.  Youn-Long Lin, "(1) A High-Performance and Memory Efficient Architecture for Integer Motion Estimation, (2) A High-Throughput Fully Hardwired CABAC Decoder for H.264/AVC, (3) Refernece Frame Access Optimization for Ultrahigh Resolution H.264/AVC Decoding," Guest Lectures in Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, Japan, November 25, 2008.

44.  Youn-Long Lin, "Financial Crisis, Dust Storm and My View of Semiconductor Industry," Department of Computer Science, National Cheng-Kung University, March 6, 2009.

45.  Youn-Long Lin, "Chipsburger: From IP/Design Reuse for SOCs to Manufacture Reuse for 3D ICs, "D43D: System Design for 3D Silicon Integration Workshop," June 17-18, 2009, LETI, Grenoble, France.

46.  Youn-Long Lin, "Chipsburger: From IP/Design Reuse for SOCs to Manufacture Reuse for 3D ICs, " Keynote Speech for "Essential Issues for Nanometer IC Design and EDA International Meeting (EIIM) -- From Taiwan Foundry and Fabless Vendor View -- " in Japan-Taiwan Semiconductor Design Summit, Kitakyushu University,  September 3, 2009

47.  Youn-Long Lin, "3D IC Design Considering Manufacturing Reuse," Waseda-NTU Workshop, January 22, 2010, NTU, Taipei, Taiwan

48.  Youn-Long Lin, "Memory Access Optimization for Ultra High Resolution Video Decoding,"  10th International Forum on Embedded Multiprocessor and Multicore (MPSOC), Gifu, Japan, June 28-July 2, 2010

49.  Youn-Long Lin, "An ICT-Enabled Better World," International Workshop on IT and Future Society, October 8-9, 2010, Jeju, Korea.

50.  Youn-Long Lin, "From Design Reuse for SOC to Manufacturing Reuse for 3D IC," Microprocessor Research Center, Peking University, November 2010, Beijing, China

51.  Youn-Long Lin, "Memory Access Optimization for Motion Compensation," Waseda University GCOE Workshop, January 29, 2010, Waseda University, Tokyo, Japan

52.  Youn-Long Lin, "From Design Reuse for SOC to Manufacturing Reuse for 3D IC," NYU-AD 3D IC Workshop, Abu Dhabi, April 2011.

53.  Youn-Long Lin, "Yield Improvement for 3D ICs with Redundant TSVs," D43D Workshop, Leti, Grenoble, France, June 2011.

54.  Youn-Long Lin, "Multiprocessor Scheduling Taking into Account Energy Harvesting and Storage,"  11th International Forum on Application-Specific Multi-processor SOC (MPSOC), Beaune, France, July 2011.

55.  Youn-Long Lin, "From Design Reuse for SOC to Manufacturing Reuse for 3D IC," The PROFIT Workshop, Hohhot, Inner Mongolia, China, August 2011.

56.  Youn-Long Lin, "Display Frame Compression for Ultra High Resolution Video," Ambient GCOE Workshop on System LSI, Kitakyushu, Japan, November 24-25, 2011.

57.  Youn-Long Lin, "Power Delivery and Scheduling under Inrush Current Constraints," D43D Workshop, Lausanne, Switzerland, June 25-27, 2012.

58.  Youn-Long Lin, "Power-Up Scheduling for Multicore SOCs,"  12th International Forum on Application-Specific Multi-processor SOC (MPSOC), Le Chateau Montebello, Quebec, Canada, July 8-13, 2012.

59.  Youn-Long Lin, "Intra-Frame Encoding for Bus Traffic and Memory Reduction,"  13th International Forum on Application-Specific Multi-processor SOC(MPSOC), Otsu, Japan, July 15-19, 2013.

60.  Youn-Long Lin, "Fast Turn-On of MTCMOS Banks Under Peak Current Constraint," ESRC-SATTI (Seoul National University & Samsung Electronics) Joint Workshop on Energy-Efficient Computing, Seoul, Korea, September 9-10, 2013.

61.  Youn-Long Lin, "Distributed Flow-Table Cache for Open Flow Switch,"  14th International Forum on Application-Specific Multi-processor SOC(MPSOC), Boudreaux, France, July 6-11, 2014.

62.  Youn-Long Lin, "SOC Implementation Challenges," Etron Technology Inc., Taipei, November 19, 2014.

63.  Youn-Long Lin, "Semiconductor Entrepreneurship," Chuang Yuan Christian University, December 2, 2014.

64.  Youn-Long Lin, Video Coding Past, Present and Future Challenges, 2015 MathWorks Asian Research Faculty Summit, November 8-9 , 2015, Shinagawa Season Terrace Conference, Tokyo, Japan.

65.  Youn-Long Lin, Value Creation, Chuang Yuan Christian University, December 7, 2015

 

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