根據題目說明：
「 You have to decide the correct bit width of the left-hand-side variable by
yourself according to the operands at the right-hand-side. 」

但是根據 IEEE standard 1364-1995
4.4 Expression bit lengths 中指出：

In the case of the addition operator, the bit length of the largest operand,
including the left-hand side of an assignment, shall be used.

Examples:

reg [15:0] a, b; // 16-bit registers
reg [15:0] sumA; // 16-bit register
reg [16:0] sumB; // 17-bit register
sumA = a + b; // expression evaluates using 16 bits
sumB = a + b; // expression evaluates using 17 bits

4.4.1 Rules for expression bit lengths 中指出：

A context-determined expression is one where the bit length of the
expression is determined by the bit length of the expression and by the
fact that it is part of another expression. For example, the bit size of
the right-hand side expression of an assignment depends on itself and the
size of the left-hand side.

也就是有些情況下，只知道 left-hand side 是不夠的
請問該如何處理？謝謝
　

ans:

為了較清楚定義此問題, 我們稍微修改了原文, 請更新.

OLD:
However, in order to simplify the problem, the left-hand-side expressions are restricted to a single variable only without bit selection (ex: a[4]), part selection (ex: a[4:2]), or any other operators. You have to decide the correct bit width of the left-hand-side variable by yourself according to the operands at the right-hand-side.

NEW:
However, in order to easily decide the bit width of whole expression, we used the bit width of the left-hand-side signal as its bit width. (ex: “a[5:0]” is 6 bits, “a” is one bit, “a[1]” is one bit).

附加檔 "CAD2004_p3.doc" is new version.
　

網頁給的測試 vcd 檔中，有如下格式：

$var wire 1 6 IN [22] $end
$var wire 1 7 IN [21] $end
$var wire 1 8 IN [20] $end
$var wire 1 9 IN [19] $end
$var wire 1 : IN [18] $end
$var wire 1 ; IN [17] $end
$var wire 1 < IN [16] $end
$var wire 1 = IN [15] $end
$var wire 1 > IN [14] $end
$var wire 1 ? IN [13] $end
$var wire 1 @ IN [12] $end
$var wire 1 A IN [11] $end
$var wire 1 B IN [10] $end
$var wire 1 C IN [9] $end
$var wire 1 D IN [8] $end
$var wire 1 E IN [7] $end
$var wire 1 F IN [6] $end
$var wire 1 G IN [5] $end
$var wire 1 H IN [4] $end
$var wire 1 I IN [3] $end
$var wire 1 J IN [2] $end
$var wire 1 K IN [1] $end
$var wire 1 L IN [0] $end

但是根據 IEEE standard 1364-1995
15.2.1 Syntax of the VCD file 中指出：

NOTES
1－ The VCD format does not support a mechanism to dump part of a vector. For
example, bits 8 to 15 (8:15) of a 16-bit vector cannot be dumped in VCD Tle;
instead, the entire vector (0:15) has to be dumped. In addition, expressions,
such as a + b, cannot be dumped in the VCD Tle.

網頁給的測式檔並不符合 standard
我們的程式該支援嗎？
是否能將所有不是 standard 但是我們程式需要支援的清楚列出？
謝謝
　

ans:

These testcases doesn't violate the standard's description. Split
some bus signals into the single bit signals is very popular to most of
simulators(they also dump the entire bus).
It is necessary to support this kind of VCD file.
　

根據題目說明：
「The logic values of all signals can be "0", "1", "X", and "Z".」

那請問需不需要處理VCD檔中 variable 是 real 的情形?
含 real 的 VCD 檔舉例如下:

$date
Feb 11, 2003 20:13:48
$end
$version
VERILOG-XL 1.6b
$end
$timescale
1s
$end

$scope module main $end
$var real 64 ! x $end
$var real 64 " y $end
$upscope $end

$enddefinitions $end
$dumpvars
r0 !
r0 "
$end
#1
r1.2 !
#2
r3.4 "
#3
r4.6 !
#4
$dumpoff
r0 !
r0 "
$end
#6
$dumpon
r6.6 !
r3.4 "
$end

請問需不需要處理? 謝謝。

ans: You don't need to support the "real" value.
　

According to section II.1, File format for the Verilog expressions to be evaluated:

“All legal Verilog operators [1] listed in Table 4-1 of IEEE 1364-1995 Verilog standard should be supported except concatenation (ex: {a,b}) and division (ex: a/b) to be compatible with Novas Debussy”

Does this means we need to support both concatenation and division, and that support should be compatible with Novas Debussy?

Or it simply means that, we do not need to support either the concatenation or division; all the other Verilog operators should be fully supported and to be compatible with Novas Debussy?

ans: You don't need to support "concatenation" or "division" operators.
　

VCD 檔中不需 support "real value"
不知 cmd 裡面是不是一樣不需 support？
還有 string 的部分，需要 support 嗎？

例如：

out[1] = a == "a string"
out[2] = b == 36.8
　

ans: You don't need to support the "real value" and "string value" for
command file.
　

從IEEE1364-1995 page 39, 我們知道，一個vector 的宣告可以是[15:0] or [1:16],
請問在VCD 檔案我們怎麼知道VCD 變數中是屬於哪一種？
如同在測試檔中：
$var wire 1 6 IN [22] $end
$var wire 1 7 IN [21] $end
$var wire 1 8 IN [20] $end
$var wire 1 9 IN [19] $end
$var wire 1 : IN [18] $end
$var wire 1 ; IN [17] $end
$var wire 1 < IN [16] $end
我們該怎麼判斷 IN 這個變數是 IN[22:16] 還是 IN [16:22] ?

另一個問題是event ordering
如 : d = a + b
a = e + c
請問我們是不是必須要先算出a 的值，再帶入d 中算?
另一個問題是：是不是所有的變數在同一個時間點只會變一次？
還有就是我們需不需要考慮下面的情況：
a [12:9] = b + c;
a [12:9] = e + f;
也就是會有一個變數或是一個變數的某個部分倍多個expression 控制？
　

ans:

1. Actually, it depends on the simulator implementation. The IEEE standard doesn't define this. We can
just use the "IN[22:16]", i.e. it will dump the MSB first.

2. You don't need to take care this kind of cases.
　

請問計算完的 evaluation results 在 VCD 裡的 type 類型是什麼?
VCD 的 type 類型有 reg, wire, integer, ...等等
是由我們自己任意設定嗎 ?

舉例, "a = b&c"
計算完成的a要存成 VCD 中的
$var wire 1 # a $end
$var reg 1 # a $end
.
.
哪一種型態呢?
　

ans: For bit type data value, you can use "wire" or "reg". For integer
data value, you need to use "integer".
　

請問如何判斷 output 的 type 是否為 integer ?

若計算式是 a = b + c，
則由題目新定義的 “a[5:0]” is 6 bits, “a” is one bit, “a[1]” is one bit，
推得 a 是 one bit 的 wire 或 reg。

若計算式是 a[31:0] = b + c，
則推得 a 是 32 bits 的 wire 或 reg。

那什麼情形下 output 的 type 才會知道是 integer 呢 ?

ans:

Since we already simply the problem(i.e. we only use the
left-hand-side to decide the bit width), the result will always be bit
type. You can just use either "wire" or "reg" for all your expression.
(If there any integer data operand in the right-hand-side, you should
convert it to 32-bits vector)

According to the test case t1.vcd,
why is there multiple entries dumped for the same signal at the same interval of time?

For example:
at time 0, the RESULT (7#) signal appears 3 times!

line 344: bxxxxxxxx 7#
line 543: bx1x0xzz0 7#
line 620: b0110zzz0 7#

How do we deal with this problem?
Which value should we use to evaluate the expressions?

The other question is that,
according to IEEE Std 1364-1995, 15.2.2 Formats of variable values (p.213),

Vector values appear in the shortest form possible: redundant bit values that result from left-extending values to fill a particular vector size is eliminated

But in the given vcd file, the redundant bits are not removed!
Do we need to remove those redundant bits when we dump the value out?

The final question, is there a sample output for the given testcase?
　

ans:

Ans1: It means this signal has "glitch" value. If your tool can take
care the "glitch", you need to evaluate all values. If you don't want to
support this feature, you can take the last one as its value.

Ans2: You don't need to remove redundant bits.

Ans3: No vcd result output for the given testcase. You can use the
"Signal->Logical Operation..." function in the Debussy's nWave to verify the
result.
　

10. [通告]

主辦單位已經將郵寄報告以及FTP上傳作品的方式公布於參賽手冊(April 22, 2004版本), 敬請盡速至競賽網頁下載. 另外, FTP站也已開放上傳作品, 也請盡速確認能否成功登入.

若有任何疑問, 請來信 cad@cs.nthu.edu.tw
謝謝
　