Tsung-Yi Ho

Publications

Books and Book Chapters:

  1. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, Full Chip Nanometer Routing Techniques, Springer, 2007.

  2. T.-Y. Ho and S.-H. Liu, "Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization" in VLSI-SoC: Forward-Looking Trends in IC and Systems Design (edited by J. L. Ayala, D. Atienza Alonso, and R. Reis), Springer, 2012 (Invited).

  3. Y. Luo, K. Chakrabarty, and T.-Y. Ho, Hardware/Software Co-Design and Optimization for Cyberphysical Integration in Digital Microfluidic Biochips, Springer, 2015.

  4. K. Hu, K. Chakrabarty, and T.-Y. Ho, Computer-Aided Design of Microfluidic Very Large Scale Integration (mVLSI) Biochips: Design Automation, Testing, and Design-for-Testability, Springer, 2017.

  5. H. Yao, Q. Wang, and T.-Y. Ho, "Smart Microfluidic Biochips: Cyberphysical Sensor Integration for Dynamic Error Recovery" in Smart Sensors at the IoT Frontier (edited by Y. Hiroto et al.), Springer, 2018 (Invited).

  6. Z. Li, K. Chakrabarty, T.-Y. Ho, and C.-Y. Lee, Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques, Springer, 2019.

 

ACM/IEEE Journal Papers:

  1. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee, "Crosstalk- and Performance- Driven Multilevel Full-Chip Routing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 24, no. 6, pp. 869-878, June 2005.

  2. T.-W. Huang, C.-H. Lin, and T.-Y. Ho, "A Contamination Aware Droplet Routing Algorithm for the Synthesis of Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 29, no. 11, pp. 1682-1695, November 2010.

  3. T.-W. Huang and T.-Y. Ho, "A Two-Stage ILP-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 30, no. 2, pp. 215-228, February 2011.

  4. S. Chou, C.-S. Han, P.-K. Huang, K.-F. Tien and T.-Y. Ho, "An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 30, no. 7, pp. 1045-1057, July 2011.

  5. T.-W. Huang, S.-Y. Yeh, and T.-Y. Ho, "A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing EWOD Chips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 30, no. 12, pp. 1786-1799, December 2011.

  6. J.-W. Lin, T.-Y. Ho, and I. H.-R. Jiang, "Reliability-driven power/ground routing for analog ICs," ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 17 Issue 1, No. 6, January 2012.

  7. K.-Y. Lin, H.-T. Lin, T.-Y. Ho, and C.-C. Tsai, "Load-Balanced Clock Tree Synthesis with Adjustable Delay Buffer Insertion for Clock Skew Reduction in Multiple Dynamic Supply Voltage Designs," ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 17 Issue 3, No. 34, June 2012.

  8. K.-T. Hsu, S. Sinha, Y.-C. Pi, and T.-Y. Ho, "A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 31, no. 10, pp. 1546-1557, October 2012.

  9. Y.-L. Hsieh, T.-Y. Ho, and K. Chakrabarty, "A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical Samples Using Digital Microfluidics," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 31, no. 11, pp. 1656-1669, November 2012.

  10. Y. Luo, K. Chakrabarty, and T.-Y. Ho, "Error Recovery in Cyberphysical Digital-Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 32, no. 1, pp. 59-72, January 2013.

  11. J.-W. Chang, S.-H. Yeh, T.-W. Huang, and T.-Y. Ho, "Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 32, no. 2, pp. 216-227, February 2013.

  12. P.-H. Wu, Mark P.-H. Lin, T.-C. Chen, and T.-Y. Ho, Y.-C. Chen, S.-R. Siao, and S.-H. Lin, "1-D Cell Generation with Printability Enhancement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 32, no. 3, pp. 419-432, March 2013.

  13. Y.-H. Chen, C.-L. Hsu, L.-C. Tsai, T.-W. Huang, and T.-Y. Ho, "A Reliability-Oriented Placement Algorithm for Reconfigurable Digital Microfluidic Biochips Using 3D Deferred Decision Making Technique," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 32, no. 8, pp. 1151-1162, August 2013.

  14. J.-W. Chang, S.-H. Yeh, T.-W. Huang, and T.-Y. Ho, "An ILP-based Routing Algorithm for Pin-Constrained EWOD Chips with Obstacle Avoidance," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 32, no. 11, pp. 1655-1667, November 2013.

  15. Y. Luo, K. Chakrabarty, and T.-Y. Ho, "Real-Time Error Recovery in Cyberphysical Digital-Microfluidic Biochips Using a Compact Dictionary," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 32, no. 12, pp. 1839-1852, December 2013.

  16. Y.-L. Hsieh, T.-Y. Ho, and K. Chakrabarty, "Biochip Synthesis and Dynamic Error Recovery for Sample Preparation Using Digital Microfluidics," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 33, no. 2, pp. 183-196, February 2014.

  17. H.-T. Lin, Y.-L. Chuang, Z.-H. Yang, and T.-Y. Ho, "Pulsed-Latch Utilization for Clock-Tree Power Optimization," IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI), vol. 22, no. 4, pp. 721-733, April 2014.

  18. Y. Luo, K. Chakrabarty, and T.-Y. Ho, "Biochemistry Synthesis on a Cyberphysical Digital Microfluidics Platform under Completion-Time Uncertainties in Fluidic Operations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 33, no. 6, pp. 903-916, June 2014.

  19. P.-H. Wu, Mark P.-H. Lin, T.-C. Chen, C.-F. Yeh, T.-Y. Ho, and B.-D. Liu, "Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 33, no. 6, pp. 879-892, June 2014.

  20. S.-H. Yeh, J.-W. Chang, T.-W. Huang, S.-T. Yu, and T.-Y. Ho, "Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 33, no. 9, pp. 1302-1315, September 2014.

  21. Sean S.-Y. Liu, C.-H. Chang, H.-M. Chen, and T.-Y. Ho, "ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 33, no. 9, pp. 1316-1327, September 2014.

  22. K. Hu, F. Yu, T.-Y. Ho, and K. Chakrabarty, "Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 33, no. 10, pp. 1463-1475, October 2014 (Best Paper Award).

  23. J.-L. Lin, P.-H. Wu, and T.-Y. Ho, “A Novel Cell Placement Algorithm for Flexible TFT Circuits with Mechanical Strain and Temperature Consideration," ACM Journal of Emerging Technologies and Computing Systems (ACM JETC), vol.11, issue 1, no. 1, September 2014.

  24. I.-C. Lin, S.-M. Syu, and T.-Y. Ho, “NBTI Tolerance and Leakage Reduction using Gate Sizing," ACM Journal of Emerging Technologies and Computing Systems (ACM JETC), vol.11, issue 1, no. 4, September 2014.

  25. Y. Luo, B. Bhattacharya, T.-Y. Ho, and K. Chakrabarty, "Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip for the Polymerase Chain Reaction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 34, no. 1, pp. 29-42, January 2015.

  26. P.-H. Wu, Mark P.-H. Lin, T.-C. Chen, C.-F. Yeh, X. Li, and T.-Y. Ho, "A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 34, no. 2, pp. 199-212, February 2015.

  27. S.-T. Yu, S.-H. Yeh, and T.-Y. Ho, "Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 34, no. 4, pp. 529-539, April 2015.

  28. T. A. Dinh, S. Yamashita, and T.-Y. Ho, "An Optimal Pin-Count Design with Logic Optimization for Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 34, no. 4, pp. 629-641, April 2015.

  29. T.-M. Tseng, B. Li, T.-Y. Ho, and U. Schlichtmann, "ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 34, no. 6, pp. 1000-1013, June 2015.

  30. H. Yao, Q. Wang, Y. Ru, T.-Y. Ho, and Y. Cai, "Integrated Flow-Control Co-Design Methodology for Flow-Based Microfluidic Biochips," IEEE Design and Test of Computers (IEEE D&T), vol. 32, no. 6, pp. 60-68, December 2015.

  31. T.-M. Tseng, B. Li, T.-Y. Ho, and U. Schlichtmann, "Storage and Caching: Synthesis of Flow-based Microfluidic Biochips," IEEE Design and Test of Computers (IEEE D&T), vol. 32, no. 6, pp. 69-75, December 2015.

  32. Z. Lee, T.-Y. Ho, and K. Chakrabarty, "Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction," ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 21 Issue 2, No. 25, February 2016.

  33. Y. Liu, S. Hu, and T.-Y. Ho, "Leveraging Strategic Detection Techniques for Smart Home Pricing Cyberattacks," IEEE Transactions on Dependable and Secure Computing (IEEE TDSC), Vol. 13, issue 2, pp. 220-235, March 2016.

  34. K. Hu, T.-Y. Ho, and K. Chakrabarty, "Wash Optimization and Analysis for Cross-Contamination Removal under Physical Constraints in Flow-Based Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 35, no. 4, pp. 559-572, April 2016.

  35. P.-H. Wu, Mark P.-H. Lin, X. Li, and T.-Y. Ho, "Parasitic-aware Common-centroid FinFET Placement and Routing for Current-ratio Matching," ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 21 Issue 3, No. 39, April 2016.

  36. H. Yao, Q. Wang, Y. Shen, T.-Y. Ho, and Y. Cai, "Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 35, no. 8, pp. 1283-1296, August 2016.

  37. T.-M. Tseng, B. Li, M. Li, T.-Y. Ho, and U. Schlichtmann, "Reliability-aware Synthesis with Dynamic Device Mapping and Fluid Routing for Flow-based Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 35, no. 12, pp. 1981-1994, December 2016.

  38. Y.-W. Wu, Y Shi, S. Roy, and T.-Y. Ho, "Obstacle-Avoiding Wind Turbine Placement for Power Loss and Wake Effect Optimization," ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 22 Issue 1, No. 5, November 2016.

  39. K. Hu, T. A. Dinh, T.-Y. Ho, and K. Chakrabarty, "Control-Layer Routing and Control-Pin Minimization for Flow-based Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 36, no. 1, pp. 55-68, January 2017.

  40. S. Bhattacharjee, S. Chatterjee, A. Banerjee, T.-Y. Ho, K. Chakrabarty, and B. B. Bhattacharya, "Adaptation of Biochemical Protocols to Handle Technology-Change for Digital Microfluidics," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 36, no. 3, pp. 370-383, March 2017.

  41. T. Y. Huang, C.-J. Chang, C.-W. Lin, S. Roy, and T.-Y. Ho, "Delay-Bounded Intra-Vehicle Network Routing Algorithm for Minimization of Wiring Weight and Wireless Transmit Power," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 36, no. 4, pp. 551-561, April 2017.

  42. Z. Li, Y.-T. Lai, P.-H. Yu, K. Chakrabarty, T.-Y. Ho, and C.-Y. Lee, "Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips," IEEE Transactions on Biomedical Circuits and Systems (IEEE TBioCAS), vol. 11, no. 3, pp. 612-616, June 2017.

  43. Z. Li, Y.-T. Lai, K. Chakrabarty, T.-Y. Ho, and C.-Y. Lee, "Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array Digital Microfluidic Biochip," IEEE Transactions on Biomedical Circuits and Systems (IEEE TBioCAS), vol. 11, no. 6, pp. 1380-1391, December 2017.

  44. Q. Wang, Y. Xu, S. Zuo, H. Yao, T.-Y. Ho, B. Li, U. Schlichtmann, and Y. Cai, "Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips," IEEE Transactions on Biomedical Circuits and Systems (IEEE TBioCAS), vol. 11, no. 6, pp. 1488-1499, December 2017.

  45. Z. Li, Kelvin Y.-T. Lai, P.-H. Yu, K. Chakrabarty, M. Pajic, T.-Y. Ho, and C.-Y. Lee, "Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 37, no.3, pp. 601-614, March 2018.

  46. G.-R. Lu, C.-H. Kuo, K.-C. Chiang, A. Banerjee, B. Bhattacharya, and T.-Y. Ho, and H.-M. Chen, "Flexible Droplet Routing in Active-Matrix Based Digital Microfluidic Biochips," ACM Transactions on Design Automation of Electronic Systems (ACM TODAES), Vol. 23 Issue 3, No. 37, April 2018.

  47. Z. Li, Kelvin Y.-T. Lai, P.-H. Yu, K. Chakrabarty, T.-Y. Ho, and C.-Y. Lee, "Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochip," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 37, no.5, pp. 968-981, May 2018.

  48. Q. Wang, Z. Hao, H. Yao, R. Wille, T.-Y. Ho, and Y. Cai, "Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 37, no.6, pp. 1157-1170, June 2018.

  49. T.-M. Tseng, M. Li, I. E. Araci, T. McAuley, B. Li, T.-Y. Ho, and U. Schlichtmann, "Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 37, no.8, pp. 1588-1601, August 2018.

  50. G.-R. Lu, G.-M. Huang, A. Banerjee, B. Bhattacharya, T.-Y. Ho, and H.-M. Chen, “On Reliability Hardening in Cyber-Physical Digital-Microfluidic Biochips," ACM Journal of Emerging Technologies and Computing Systems (ACM JETC), vol.14, issue 3, no. 34, October 2018.

  51. K. Yang, H. Yao, T.-Y. Ho, K. Xin, and Y. Cai, "AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 37, no.12, pp. 3042-3055, December 2018.

  52. W.-C. Chung, P.-Y. Cheng, Z. Li, and T.-Y. Ho, "Module Placement under Completion Time Uncertainty in Micro-Electrode-Dot-Array Digital Microfluidic Biochips," IEEE Transactions on Multi-Scale Computing Systems (IEEE TMSCS), vol. 4, no.4, pp. 811-821, December 2018.

  53. Z. Zhong, Z. Li, K. Chakrabarty, T.-Y. Ho, and C.-Y. Lee, "Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques," IEEE Transactions on Biomedical Circuits and Systems (IEEE TBioCAS), vol. 13, no. 2, pp. 292-313, April 2019.

  54. S. Bhattacharjee, A. Banerjee, T.-Y. Ho, K. Chakrabarty, and B. B. Bhattacharya, "Efficient Generation of Dilution Gradients with Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 38, no.5, pp. 874-887, May 2019.

  55. Q. Zhao, W. Sun, J. Zhao, J. Zhao, H. Yao, T.-Y. Ho, X. Guo, H. Yang, and Y. Liu, "Design Methodology for TFT Based Pseudo-CMOS Logic Array with Multi-Layer Interconnection Architecture and Optimization Algorithms," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), vol. 38, no.12, pp. 2043-2057, November 2019.

  56. J. Weng, T.-Y. Ho, W. Ji, P. Liu, M. Bao, and H. Yao, "URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips," accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

  57. Q. Wang, W. Ji, Z. Li, H. Cheong, O.-S. Kwon, H. Yao, T.-Y. Ho, K. Shin, B. Li, U. Schlichtmann, and Y. Cai, "Integrated Control-Fluidic CoDesign Methodology for Paper-Based Digital Microfluidic Biochips," accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

  58. X. Huang, T.-Y. Ho, K. Chakrabarty, and W. Guo, "Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips," accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

  59. Y. Zhu, X. Huang, B. Li, T.-Y. Ho, Q. Wang, H. Yao, R. Wille, and U. Schlichtmann, "MultiControl: Advanced Control Logic Synthesis for Flow-Based Microfluidic Biochips," accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

  60. T.-C. Liang, Y.-S. Chan, T.-Y. Ho, K. Chakrabarty, and C.-Y. Lee, "Multi-Target Sample Preparation Using MEDA Biochips," accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

  61. W. Ji, T.-Y. Ho, J. Wang, and H. Yao, "Microfluidic Design for Concentration Gradient Generation using Artificial Neural Network," accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

  62. C. Liu, B. Li, B. Bhattacharya, K. Chakrabarty, T.-Y. Ho, and U. Schlichtmann, "Test Generation for Flow-Based Microfluidic Biochips with General Architectures," accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

  63. L. Shao, W. Li, T.-Y. Ho, S. Roy, and H. Yao, " Lookup Table Based Fast Reliability-Aware Sample Preparation using Digital Microfluidic Biochips," accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD).

 

Other Journal Papers:

  1. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multilevel Routing with Jumper Insertion for Antenna Avoidance," Elsevier Integration: The VLSI Journal, vol. 39, Issue 4, pp. 420-432, July 2006 (EI/SCI).

  2. T.-Y. Ho, "PIXAR: A Performance-Driven X-Architecture Router Based on a Novel Multilevel Framework," Elsevier Integration: The VLSI Journal, vol. 42, Issue 3, pp. 400-408, June 2009 (EI/SCI).

  3. P.-H. Wu and T.-Y. Ho, "Bus-Driven Floorplanning with Bus Pin Assignment and Deviation Minimization," Elsevier Integration: The VLSI Journal, Vol. 45, Issue 4, pp. 405-426, September 2012 (EI/SCI).

  4. P.-H. Wu and T.-Y. Ho, "Bus-Driven Floorplanning with Thermal Consideration," Elsevier Integration: The VLSI Journal, Vol. 46, Issue 4, pp. 369-381, September 2013 (EI/SCI).

  5. T. A. Dinh, S. Yamashita, T.-Y. Ho, and Y. Hara-Azumi, "Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips," IEICE Transactions on Fundamentals of Electronics, Vol. E96-A, No. 12, pp. 2668-2679, December 2013 (EI/SCI).

  6. T.-Y. Ho, "Design Automation for Digital Microfluidic Biochips," IPSJ Transactions on System LSI Design Methodology, Vol. 7, pp. 16-26, February 2014 (Invited Paper) (EI/SCI).

  7. S.-T. Yu and T.-Y. Ho, "Chip-Level Design for Digital Microfluidic Biochips," International Journal of Automation and Smart Technology, Vol. 4, No. 4, pp. 202-207, 2014 (Invited Paper) (EI/SCI).

  8. T. A. Dinh, S. Yamashita, and T.-Y. Ho, "A Fully-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips," IEICE Transactions on Fundamentals of Electronics, Vol. E99-A, No. 2, pp. 570-578, February 2016 (EI/SCI).

  9. J.-D. Li, C.-H. Kuo, G.-R. Lu, S.-J. Wang, S.-M. Li, T.-Y. Ho, H.-M. Chen, and S. Hu " Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips," Elsevier Microelectronics Journal, Vol. 83, pp. 185-196, March 2019 (EI/SCI).

  10. V. Agarwal, A. Singla, M. Samiuddin, S. Roy, T.-Y. Ho, I. Sengutpa, and B. Bhattacharya "Scheduling Algorithms for Reservoir- and Mixer-Aware Sample Preparation with Microfluidic Biochips," Elsevier Integration: The VLSI Journal, Vol. 65, pp. 428-443, July 2019 (EI/SCI).

  11. H.-T.-Y. Cheng, S.-C. Lo, C.-C. Huang, T.-Y. Ho, Y.-T. Yang, "Detailed profiling of carbon fixation of in silico synthetic autotrophy with reductive tricarboxylic acid cycle and Calvin-Benson-Bassham cycle in Esherichia coli using hydrogen as an energy source," Elsevier Synthetic and Systems Biotechnology, Vol. 4, Issue 3, pp. 165-172, September 2019 (EI/SCI).

 

ACM/IEEE Conference Papers:

*: High Impact Conferences in "CSRankings: Computer Science Rankings"

  1. *T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee, "A Fast Crosstalk- and Performance-Driven Multilevel Routing System," Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2003), pp. 382-387, San Jose, CA, Nov. 2003.

  2. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multilevel Routing with Antenna Avoidance," Proceedings of ACM International Symposium on Physical Design (ISPD-2004), pp. 34-40, Phoenix, AZ, April 2004.

  3. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multilevel Routing with Jumper Insertion for Antenna Avoidance," Proceedings of IEEE International SOC Conference (SOCC-2004), pp. 63-66, Santa Clara, CA, September 2004.

  4. *T.-Y. Ho, C.-F. Chang, Y.-W. Chang, and S.-J. Chen, "Multilevel Full-Chip Routing for the X-Based Architecture," Proceedings of ACM/IEEE Design Automation Conference (DAC-2005), pp. 597-602, Anaheim, CA, June 2005. (Best Paper Nomination)  

  5. T.-Y. Ho, "A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router," Proceedings of IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS-2008), pp. 209-218, Lisbon, Portugal, September 2008. Lecture Notes in Computer Science (LNCS), Springer.

  6. S. Chou and T.-Y. Ho, "OAL: An Obstacle-Aware Legalization in Standard Cell Placement with Displacement Minimization," Proceedings of IEEE International SOC Conference (SOCC-2009), pp. 329-332, Belfast, Northern Ireland, September 2009.

  7. T.-W. Huang and T.-Y. Ho, "A Fast Routability- and Performance-Driven Droplet Routing Algorithm for Digital Microfluidic Biochips," Proceedings of IEEE International Conference on Computer Design (ICCD-2009), pp. 445-450, Lake Tahoe, CA, October 2009.

  8. *T.-W. Huang, C.-H. Lin, and T.-Y. Ho, "A Contamination Aware Droplet Routing Algorithm for Digital Microfluidic Biochips," Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), pp. 151-156 , San Jose, CA, November 2009.

  9. T.-W. Huang and T.-Y. Ho, "A Two-Stage ILP-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips," Proceedings of ACM International Symposium on Physical Design (ISPD-2010), pp. 201-208, San Francisco, CA, March 2010.

  10. B.-S. Wu and T.-Y. Ho, ''Bus-Pin-Aware Bus-Driven Floorplanning," Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI-2010), pp. 27-32, Providence, RI, May 2010.

  11. T.-Y. Ho, S.-H. Liu, and S.-M. Tseng, "Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization," Proceedings of IEEE/IFIP International Conference on VLSI and System-on- Chip (VLSI-SoC-2010), pp. 369-374, Madrid, Spain, September 2010.

  12. *T.-W. Huang, S.-Y. Yeh, and T.-Y. Ho, "A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast Electrode-Addressing EWOD Chips," Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), pp. 425-431, San Jose, CA, November 2010.

  13. *T.-Y. Ho, J. Zeng, and K. Chakrabarty, "Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore," Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2010), pp. 578-585, San Jose, CA, November 2010.  

  14. K.-Y. Lin, H.-T. Lin, and T.-Y. Ho, "An Efficient Algorithm of Adjustable Delay Buffer Insertion for Clock Skew Minimization in Multiple Dynamic Supply Voltage Designs," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2011), pp. 825-830, Yokohama, Japan, January 2011 (Best Paper Nomination).

  15. Y.-L. Hsieh and T.-Y. Ho, "Automated Physical Design of Microchip-Based Capillary Electrophoresis Systems," Proceedings of IEEE International Conference on VLSI Design (VLSI-2011), pp. 165-170, Chennai, India, January 2011.

  16. *T.-W. Huang, H.-Y. Su, and T.-Y. Ho, "Progressive Network-Flow Based Power-Aware Broadcast Addressing for Pin-Constrained Digital Microfluidic Biochips," Proceedings of ACM/IEEE Design Automation Conference (DAC-2011), pp. 741-746, San Diego, CA, June 2011.

  17. *K.-T. Hsu, S. Sinha, Y.-C. Pi, C. Chiang, and T.-Y. Ho, "A Distributed Algorithm for Layout Geometry Operations," Proceedings of ACM/IEEE Design Automation Conference (DAC-2011), pp. 182-187, San Diego, CA, June 2011.

  18. P.-H. Yuh, C. C.-Y. Lin, T.-W. Huang, T.-Y. Ho, C.-L. Yang, and Y.-W. Chang, "A SAT-Based Routing Algorithm for Cross-Referencing Biochips," Proceedings of ACM International Workshop on System Level Interconnect Prediction (SLIP-2011), pp. 1-7, San Diego, CA, June 2011.

  19. P.-H. Wu and T.-Y. Ho, "Thermal-Aware Bus-Driven Floorplanning," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED-2011), pp. 205-210, Fukuoka, Japan, August 2011.

  20. H.-T. Lin, Y.-L. Chuang, and T.-Y. Ho, "Pulsed-Latch-Based Clock Tree Migration for Dynamic Power Reduction," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED-2011), pp. 39-44, Fukuoka, Japan, August 2011.

  21. T.-W. Huang, Y.-Y. Lin, J.-W. Chang, and T.-Y. Ho, "Chip-Level Design and Optimization for Digital Microfluidic Biochips," Proceedings of IEEE International Midwest Symposium on Circuit and System (MWSCAS-2011), pp. 1-4, Seoul, Korea, August 2011.

  22. T.-W. Huang, Y.-Y. Lin, J.-W. Chang, and T.-Y. Ho, "Recent Research and Emerging Challenges in Design and Optimization for Digital Microfluidic Biochips," Proceedings of IEEE International SOC Conference (SOCC-2011), pp. 12-17, Taipei, Taiwan, September 2011.

  23. K. Chakrabarty, P. Pop, and T.-Y. Ho, "Digital Microfluidic Biochips: Functional Diversity, More than Moore, and Cyberphysical Systems," Proceedings of IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS-2011), pp. 377, Taipei, Taiwan, October 2011.

  24. T.-Y. Ho, P. Pop, and K. Chakrabarty, "Microfluidic biochips: Recent research and emerging challenges," Proceedings of IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS-2011), pp. 335-343, Taipei, Taiwan, October 2011.

  25. *Y.-L. Chuang, H.-T. Lin, T.-Y. Ho, Y.-W Chang, and D. Marculescu, "PRICE: Power Reduction by Placement and Clock-Network Co-Synthesis for Pulsed-Latch Designs," Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), pp. 85-90, San Jose, CA, November 2011.

  26. *T.-W. Huang, T.-Y. Ho, and K. Chakrabarty, "Reliability-Oriented Broadcast Electrode-Addressing for Pin- Constrained Digital Microfluidic Biochips," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2011), pp. 448-455, San Jose, CA, November 2011.

  27. Y.-L. Hsieh, T.-Y. Ho, and K. Chakrabarty, "On-Chip Biochemical Sample Preparation Using Digital Microfluidics," Proceedings of IEEE Biomedical Circuits & Systems Conference (BioCAS-2011), pp. 297-300, San Diego, CA, November 2011.

  28. J.-W. Chang, T.-W. Huang, and T.-Y. Ho, "An ILP-based Obstacle-Avoiding Routing Algorithm for Pin-Constrained EWOD Chips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2012), pp. 67-72, Sidney, Australia, January 2012 (Best Paper Nomination).

  29. T.-W. Huang, J.-W. Chang, and T.-Y. Ho, "Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips," Proceedings of ACM International Symposium on Physical Design (ISPD-2012), pp. 49-56, Napa, California, March 2012.

  30. Y. Luo, K. Chakrabarty, and T.-Y. Ho, "A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips", Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2012), pp. 1239-1244, Dresden, Germany, March 2012.

  31. S.-J. Jiang, J.-L. Wu, and T.-Y. Ho, "A Nonlinear Optimization Methodology for Resistor Matching in Analog Integrated Circuits", Proceedings of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT-2012), pp. 1-4, Hsinchu, Taiwan, April 2012.

  32. *Y. Luo, K. Chakrabarty, and T.-Y. Ho, "Dictionary-Based Error Recovery in Cyberphysical Digital-Microfluidic Biochips," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2012), pp. 369-376, San Jose, CA, November 2012.

  33. *P.-H. Wu, P.-H. Lin, Y.-R. Chen, B.-S. Chou, T.-C. Chen, T.-Y. Ho, and B.-D. Liu, "Performance-driven Analog Placement Considering Monotonic Current Paths," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2012), pp. 613-619, San Jose, CA, November 2012.

  34. *S.-H. Yeh, J.-W. Chang, T.-W. Huang, and T.-Y. Ho, "Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2012), pp. 353-360, San Jose, CA, November 2012.

  35. Y.-L. Hsieh, T.-Y. Ho, and K. Chakrabarty, "Design Methodology for Sample Preparation on Digital Microfluidic Biochips," Proceedings of IEEE International Conference on Computer Design (ICCD-2012), pp. 189-194, Montreal, CA, September 2012.

  36. T.-Y. Ho, "Design Automation for Digital Microfluidic Biochips: From Fluidic-Level Toward Chip-Level," Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT-2012), pp. 1-4, Xi’an, China, October 2012. (Invited Paper)

  37. T.-Y. Ho, "Top-Down Synthesis Methodology for Flow-Based Microfluidic Biochips," Proceedings of IEEE International Symposium on Electronic Designs (ISED-2012), pp. 1, Kolkata, India, December 2012. (Keynote Speech)

  38. J.-L. Lin, P.-H. Wu, and T.-Y. Ho, "A Novel Cell Placement Algorithm for Flexible TFT Circuit with Mechanical Strain and Temperature Consideration," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2013), pp. 491-496, Yokohama, Japan, January 2013.

  39. T. A. Dinh, S. Yamashita, T.-Y. Ho, Yuko Hara-Azumi, "A Clique-Based Approach to Find Binding and Scheduling Result in Flow-Based Microfluidics Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2013), pp. 199-204, Yokohama, Japan, January 2013.

  40. W. H. Minhass, Paul Pop, Jan Madsen, T.-Y. Ho, "Control Synthesis of the Flow-Based Microfluidic Large-Scale Integration Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2013), pp. 205-212, Yokohama, Japan, January 2013.

  41. K.-H. Tseng, S.-C. You, W. H. Minhass, T.-Y. Ho, Paul Pop, "A Network-Flow Based Valve-Switching Aware Binding Algorithm for Flow-Based Microfluidic Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2013), pp. 213-218, Yokohama, Japan, January 2013.

  42. K.-H. Tseng, S.-C. You, J. Y. Liu, and T.-Y. Ho, "A Top-Down Synthesis Methodology for Flow-Based Microfluidic Biochips Considering Valve-Switching Minimization," Proceedings of ACM International Symposium on Physical Design (ISPD-2013), pp. 123-129, Lake Tahoe, NV, March 2013.

  43. Z.-H. Yang and T.-Y. Ho, "Timing-Aware Clock Gating of Pulsed-Latch Circuits for Low Power Design," Proceedings of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT-2013), pp. 1-4, Hsinchu, Taiwan, April 2013.

  44. K. Hu, T.-Y. Ho, and K. Chakrabarty, "Testing of Flow-Based Microfluidic Biochips," Proceedings of IEEE VLSI Test Symposium (VTS-2013), pp. 1-6, Berkeley, CA, April 2013. (Best Paper Award)

  45. S.-J. Jiang and T.-Y. Ho, "A Rapid Analog Amendment Framework Using the Incremental Floorplanning Technique," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2013), pp. 1716-1719, Beijing, China, May 2013.

  46. T.-M. Tseng, B. Li, T.-Y. Ho, and U. Schlichtmann, "Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation," Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI-2013), pp. 323-324, Paris, France, May 2013.

  47. *Y. Luo, K. Chakrabarty, and T.-Y. Ho, "Design of Cyberphysical Digital-Microfluidic Biochips under Completion-Time Uncertainties in Fluidic Operations," Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), pp.44-49, Austin, TX, June 2013.

  48. P.-H. Wu, P.-H. Lin, T.-Y. Ho, and Y.-C. Chen, "Lithography-Aware 1-Dimensional Cell Generation," Proceedings of IEEE European Conference on Circuit Theory and Design (ECCTD-2013), pp. 1-4, Dresden, Germany, September 2013.

  49. *T.-M. Tseng, B. Li, T.-Y. Ho, and U. Schlichtmann, "Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2013), pp. 713-720, San Jose, CA, November 2013.

  50. *Y. Luo, B. Bhattacharya, T.-Y. Ho, and K. Chakrabarty, "Optimization of Polymerase Chain Reaction on a Cyberphysical Digital Microfluidic Biochip," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2013), pp. 622-629, San Jose, CA, November 2013.

  51. S. Bhattacharjee, A. Banerjee, T.-Y. Ho, K. Chakrabarty, and B. Bhattacharya, "On Producing Linear Dilution Gradient of a Sample with a Digital Microfluidic Biochip," Proceedings of IEEE International Symposium on Electronic System Designs (ISED-2013), pp., Singapore, December 2013.

  52. S.-Y. Bai, P.-H. Wu, and T.-Y. Ho, "A Topology-based ECO Routing Methodology for Mask Cost Minimization," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2014), pp. 507-512, Singapore, January 2014.

  53. K. Hu, T.-Y. Ho, and K. Chakrabarty, "Wash Optimization for Cross-Contamination Removal in Flow-Based Microfluidic Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2014), pp. 244-249, Singapore, January 2014.

  54. T. A. Dinh, S. Yamashita, and T.-Y. Ho, "A Network-Flow-Based Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2014), pp. 225-230, Singapore, January 2014. (Best Paper Nomination)

  55. S.-S. Wu, K. W. Wang, Sai Manoj P. D., T.-Y. Ho and H. Yu, "A Thermal Resilient Integration of Many-core Microprocessor and Main Memory by 2.5D TSI I/Os," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2014), pp. 1-4, Dresden, Germany, March 2014.

  56. T. A. Dinh, S. Yamashita, and T.-Y. Ho, "A Logic Integrated Optimal Pin-Count Design for Digital Microfluidic Biochips," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2014), pp. 1-6, Dresden, Germany, March 2014.

  57. S.-T. Yu, S.-H. Yeh, and T.-Y. Ho, "Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips," Proceedings of ACM International Symposium on Physical Design (ISPD-2014), pp. 133-140, Petaluma, CA, March 2014.

  58. K. Hu, T.-Y. Ho, and K. Chakrabarty, "Test Generation and Design-for-Testability for Flow-Based mVLSI Microfluidic Biochips," Proceedings of IEEE VLSI Test Symposium (VTS-2014), pp. 1-6, Napa, CA, April 2014. (Best Paper Nomination)

  59. C.-W. Chen, P.-H. Wu, and T.-Y. Ho, "Triangle-based Process Hotspot Classification with Dummification in EUVL," Proceedings of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT-2014), pp., Hsinchu, Taiwan, April 2014.

  60. *Y. Shen, Q. Wang, H. Yao, T.-Y. Ho, and Y. Cai, "Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips," Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), pp. 141:1-6, San Francisco, CA, June 2014.

  61. *C.-X. Lin, C.-H. Liu, I.-C. Chen, D.-T. Lee, and T.-Y. Ho, "An Efficient Bi-criteria Flow Channel Routing Algorithm For Flow-based Microfluidic Biochips," Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), pp. 142:1-6, San Francisco, CA, June 2014.

  62. *K. Oliver, R. Wille, T.-Y. Ho, and R. Drechsler, "Exact One-pass Synthesis of Digital Microfluidic Biochips," Proceedings of ACM/IEEE Design Automation Conference (DAC-2014), pp. 143:1-6, San Francisco, CA, June 2014.

  63. Z. Lee, T.-Y. Ho, and K. Chakrabarty, "Optimization of Heaters in a Digital Microfluidic Biochip for the Polymerase Chain Reaction," Proceedings of IEEE International Workshop on Thermal Investigations of ICs and Systems (THERMINIC-2014), pp., Greenwich, UK, September 2014.

  64. K. Hu, T. A. Dinh, T.-Y. Ho, and K. Chakrabarty, "Control-Layer Optimization for Flow-Based mVLSI Microfluidic Biochips," Proceedings of ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2014), pp. 1-10, New Delhi, India, October 2014.

  65. *Y. Liu, S. Hu, and T.-Y. Ho, "Cyber Attack of Electricity Pricing in Smart Home," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2014), pp. 183-190, San Jose, CA, November 2014.

  66. Z. Li, T. A. Dinh, T.-Y. Ho, and K. Chakrabarty, "Reliability-driven pipelined scan-like testing of digital microfluidic biochips," Proceedings of IEEE Asian Test Symposium (ATS-2014), pp. 57-62, Hangchou, China, November 2014.

  67. S. Roy, C.-R. Wu, and T.-Y. Ho, "Recent Trends in Chip-Level Design Automation for Digital Microfluidic Biochips,"Proceedings of IEEE International Symposium on Integrated Circuits (ISIC-2014), pp. 1-4, Singapore, December 2014.

  68. Y.-W. Wu, S. Roy, Y. Shi, and T.-Y. Ho, "Obstacle-Avoiding Wind Turbine Placement for Power-Loss and Wake-Effect Optimization," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2015), pp. 202-207, Japan, January 2015.

  69. T.-Y. Huang, S. Roy, C.-W. Lin, and T.-Y. Ho, "Intra-Vehicle Network Routing Algorithm for Weight and Wireless Transmit Power Minimization," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2015), pp. 273-278, Japan, January 2015. (Best Paper Nomination)

  70. Z. Li, T.-Y. Ho, and K. Chakrabarty, "Design and Optimization of 3D Digital Microfluidic Biochips for the Polymerase Chain Reaction," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2015), pp. 184-189, Japan, January 2015.

  71. P.-H. Wu, Mark P.-H. Lin, X. Li, and T.-Y. Ho, "Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment," Proceedings of ACM International Symposium on Physical Design (ISPD-2015), pp. 25-31, Monterey, CA, March 2015.

  72. Q. Wang, W. He, H. Yao, T.-Y. Ho, and Y. Cai, "SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips," Proceedings of ACM International Symposium on Physical Design (ISPD-2015), pp. 49-56, Monterey, CA, March 2015.

  73. T. A. Dinh, S. Yamashita, T.-Y. Ho, and K. Chakrabarty, "Testing of Digital Microfluidic Biochips with Arbitrary Layouts," Proceedings of IEEE European Test Symposium (ETS-2015), pp. 1-2, Cluj Napoca, Romania, April 2015.

  74. *H. Yao, T.-Y. Ho, and Y. Cai, "CORLA: A New Control Channel Routing Flow with Length Matching Constraint for Flow-Based Microfluidic Biochips," Proceedings of ACM/IEEE Design Automation Conference (DAC-2015), pp. 141:1-6, San Francisco, CA, June 2015.

  75. *T.-M. Tseng, B. Li, T.-Y. Ho, and U. Schlichtmann, "Reliability-aware Synthesis for Flow-based Microfluidic Biochips by Dynamic-device Mapping," Proceedings of ACM/IEEE Design Automation Conference (DAC-2015), pp. 142:1-6, San Francisco, CA, June 2015.

  76. *W. Wen, C.-R. Wu, X. Hu, B. Liu, T.-Y. Ho, X. Li, and Y. Chen, "LNCS: An EDA Framework for Large Scale Hybrid Neuromorphic Computing Systems," Proceedings of ACM/IEEE Design Automation Conference (DAC-2015), pp., 12:1-6 San Francisco, CA, June 2015. (Best Paper Nomination)

  77. W. Wen, C.-R. Wu, X. Hu, B. Liu, T.-Y. Ho, X. Li, and Y. Chen, "EDA Challenges for Memristor-Crossbar based Neuromorphic Computing," Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI-2015), pp. 185-188, Pittsburgh, PA, May 2015.

  78. P.-H. Wu, P.-H. Lin, and T.-Y. Ho, "Analog Layout Synthesis with Knowledge Mining," Proceedings of IEEE European Conference on Circuit Theory and Design (ECCTD-2015), pp. 1-4, Trondheim, Norway, August 2015.

  79. K. Hu, T.-Y. Ho, and K. Chakrabarty, "Flow-based biochips: Design for reliability and cross-contamination avoidance", Proceedings of IEEE Engineering in Medicine and Biology Conference (EMBC-2015), pp., Milan, Italy, August 2015.

  80. T. A. Dinh, S. Yamashita, T.-Y. Ho, and K. Chakrabarty, "A General Testing Method for Digital Microfluidic Biochips under Physical Constraints," Proceedings of IEEE International Test Conference (ITC-2015), pp. 1-8, Anaheim, CA, October 2015.

  81. T.-Y. Ho, W. Grover, S. Hu, and K. Chakrabarty, "Cyber-physical Integration in Programmable Microfluidic Biochips," Proceedings of IEEE International Conference on Computer Design (ICCD-2015), pp. 224-227, New York, NY, October 2015.

  82. T.-Y. Ho, S. Yamashita, A. Banerjee, and S. Roy, "Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences," Proceedings of IEEE International Conference on VLSI Design (VLSI-2016), pp. 59-62, Kolkata, India, January 2016.

  83. Y.-H. Su, T.-Y. Ho, and D. T. LEE, " A Routability-Driven Flow Routing Algorithm for Programmable Microfluidic Devices," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2016), pp. 605-610, Macao, January 2016.

  84. C.-R. Wu, W. Wen, T.-Y. Ho, and Y. Chen, "Thermal Optimization for Memristor-Based Hybrid Neuromorphic Computing Systems," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2016), pp. 274-279, Macao, January 2016.

  85. Q. Wang, Y. Ru, H. Yao, T.-Y. Ho, and Y. Cai, "Sequence-Pair-Based Placement and Routing for Flow-Based Microfluidic Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2016), pp. 587-592, Macao, January 2016.

  86. J.-D. Lee, S.-M. Lee, S.-J. Wang, and T.-Y. Ho, "Congestion- and Timing-Driven Droplet Routing for Pin-Constrained Paper-Based Microfluidic Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2016), pp. 593-598, Macao, January 2016.

  87. M. Li, T.-M. Tseng, B. Li, T.-Y. Ho, and U. Schlichtmann "Sieve-valve-aware Synthesis of Flow-based Microfluidic Biochips Considering Specific Biological Execution Limitations," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2016), pp. 624-629, Dresden, Germany, March 2016.

  88. J.-D. Lee, S.-M. Lee, S.-J. Wang, and T.-Y. Ho, "Test and Diagnosis of Paper-Based Microfluidic Biochips," Proceedings of IEEE VLSI Test Symposium (VTS-2016), pp. 1-6, Las Vegas, NV, April 2016.

  89. *T.-M. Tseng, M. Li, B. Li, T.-Y. Ho, and U. Schlichtmann, "Columba: Co-Layout Synthesis for Continuous-Flow Microfluidic Biochips," Proceedings of ACM/IEEE Design Automation Conference (DAC-2016), pp., Austin, TX, June 2016.

  90. *Z. Li, Y-.J. Lee, T.-Y. Ho, C.-Y. Lee, and K. Chakrabarty, "High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips," Proceedings of ACM/IEEE Design Automation Conference (DAC-2016), pp., Austin, TX, June 2016.

  91. *Z. Li, Kelvin Y.-T. Lai, P.-H. Yu, K. Chakrabarty, M. Pajic, T.-Y. Ho, and C.-Y. Lee, "Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2016), pp. 105, Austin, TX, November 2016.

  92. *Q. Wang, Z. Li, O.-S. Kwon, H. Yao, T.-Y. Ho, K. Shin, B. Li, U. Schlichtmann, and Y. Cai, " Control-Fluidic CoDesign for Paper-Based Digital Microfluidic Biochips," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2016), pp. 103, Austin, TX, November 2016.

  93. Z. Li, Y-.J. Lee, T.-Y. Ho, C.-Y. Lee, and K. Chakrabarty, "Built-In Self-Test for Micro- Electrode-Dot-Array Digital Microfluidic Biochips," Proceedings of IEEE International Test Conference (ITC-2016), pp. 1-10, Fort Worth, TX, November 2016.

  94. C.-H. Kuo, G.-R. Lu, T.-Y. Ho, H.-M. Chen, and S. Hu, "Placement Optimization of Cyber-Physical Digital Microfluidic Biochips," Proceedings of IEEE Biomedical Circuits & Systems Conference (BioCAS-2016), pp., Shanghai, October 2016.

  95. S. Mitra, M. Das, A. Banerjee, K. Datta, and T.-Y. Ho, "A Verification Guided Approach for Selective Transformations for Approximate Computing," Proceedings of IEEE Asian Test Symposium (ATS-2016), pp., Hiroshima, Japan, November 2016.

  96. Z. Chen, P. Zhou, T.-Y. Ho, and Y. Jin, "How Secure is Split Manufacturing in Preventing Hardware Trojan?," Proceedings of IEEE Asian Hardware Security and Trust Symposium (AsianHOST-2016), pp., Yilan, Taiwan, December 2016.

  97. Grimmer, Q. Wang, H. Yao, T.-Y. Ho, and R. Wille, "Close-to-Optimal Placement and Routing for Continuous-Flow Microfluidic Biochips,"Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2017), pp., Japan, January 2017.

  98. V. Agarwal, A. Singla, M. Samiuddin, S. Roy, T.-Y. Ho, I. Sengupta, and B. Bhattacharya, "Reservoir and Mixer Constrained Scheduling for Sample Preparation on Digital Microfluidic Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2017), pp., Japan, January 2017.

  99. C.-W. Hsieh, Z. Li, and T.-Y. Ho, "Privacy Prevention of Digital Microfluidic Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2017), pp., Japan, January 2017.

  100. G.-R. Lu, G.-M. Huang, A. Banerjee, B. Bhattacharya, T.-Y. Ho, and H.-M. Chen, "On Reliability Hardening in Cyber-Physical Digital Microfluidic Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2017), pp., Japan, January 2017.

  101. Q. Wang, S. Zuo, H. Yao, T.-Y. Ho, B. Li, U. Schlichtmann, and Y. Cai, "Hamming-Distance-Based Switching Order Optimization Method for Multiplexing in Flow-Based Microfluidic Biochips,"Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2017), pp., Japan, January 2017.

  102. W.-L. Huang, A. Gupta, S. Roy, T.-Y. Ho, and P. Pop, "Fast Architecture-Level Synthesis of Fault-Tolerant Flow-Based Microfluidic Biochips," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2017), pp., Lausanne, Switzerland, March 2017.

  103. C. Liu, B. Li, B. Bhattacharya, A. Gupta, K. Chakrabarty, T.-Y. Ho, and U. Schlichtmann, "Testing Microfluidic Fully Programmable Valve Arrays (FPVAs), " Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2017), pp., Lausanne, Switzerland, March 2017.

  104. Y.-J. Chen, S. Sharma, S. Roy, and T.-Y. Ho, "Scheduling and Optimization of Genetic Logic Circuits on Flow-Based Microfluidic Biochips," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2017), pp., Lausanne, Switzerland, March 2017.

  105. L. Shao, Y. Yang, H. Yao, and T.-Y. Ho, "LUTOSAP: Lookup-Table-Based Online Sample Preparation in Microfluidic Biochips," Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI-2017), pp., Banff, Canada, May 2017.

  106. *M. Li, T.-M. Tseng, B. Li, T.-Y. Ho, and U. Schlichtmann, "Component-Oriented High-Level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling," Proceedings of ACM/IEEE Design Automation Conference (DAC-2017), pp., Austin, TX, June 2017.

  107. *C. Liu, B. Li, H. Yao, P. Pop, T.-Y. Ho, and U. Schlichtmann, "Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage," Proceedings of ACM/IEEE Design Automation Conference (DAC-2017), pp., Austin, TX, June 2017.

  108. Z. Li, Y-.T. Lai, K. Chakrabarty, ­T.-Y. Ho, and C.-Y. Lee, "Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips," Proceedings of IEEE Annual Symposium on VLSI (ISVLSI-2017), pp. , Bochum, Germany, July 2017.

  109. J.-D. Lee, S.-J. Wang, S.-M. Lee, and T.-Y. Ho, "Design-for-Testability for Paper-Based Microfluidic Biochips," Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT-2017), pp. 1, Cambridge, UK, October 2017.

  110. G.-R. Lu, B. Bhattacharya, T.-Y. Ho, and H.-M. Chen, "Multi-Level Droplet Routing in Active-Matrix Based Digital Microfluidic Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2018), pp., Jeju, South Korea, January 2018.

  111. Grimmer, B. Klepic, and, T.-Y. Ho, "Sound Valve-Control for Programmable Microfluidic Devices," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2018), pp., Jeju, South Korea, January 2018.

  112. W. Sun, Y. Huang, Q. Zhao, F. Qiao, T.-Y. Ho, X. Guo, G. Yang, and Y. Liu, "Mechanical Strain and Temperature Aware Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2018), pp., Jeju, South Korea, January 2018.

  113. G.-R. Lai, C.-Y. Lin, and T.-Y. Ho, "Pump-Aware Flow Routing Algorithm for Programmable Microfluidic Devices," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2018), pp., Dresden, Germany, March 2018.

  114. J.-L. Wu, J.-D. Li, S.-M. Li, S.-J. Wang, and T.-Y. Ho, "SOLAR: Simultaneous Optimization of Control-Layer Pins Placement and Channel Routing in Flow-Based Microfluidic Biochips", Proceedings of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT-2018), pp. 1-4, Hsinchu, Taiwan, April 2018.

  115. *T.-M. Tseng, M. Li, D. Freitas, A. Mongersun, E. Araci, T.-Y. Ho, and U. Schlichtmann, "Columba S: A Scalable Co-Layout Design Automation Tool for Microfluidic Large-Scale Integration," Proceedings of ACM/IEEE Design Automation Conference (DAC-2018), pp., San Francisco, CA, June 2018.

  116. *C. Liu, B. Li, T.-Y. Ho, K. Chakrabarty, and U. Schlichtmann, "Design-for-Testability for Continuous-Flow Microfluidic Biochips," Proceedings of ACM/IEEE Design Automation Conference (DAC-2018), pp., San Francisco, CA, June 2018.

  117. C. Liu, B. Li, B. B. Bhattacharya, K. Chakrabarty, T.-Y. Ho, and U. Schlichtmann, "Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration", Proceedings of IEEE International Conference on IC Design and Technology (ICICDT-2018), pp. Italy, June 2018.

  118. T.-Y. Ho, "Design Automation and Test for Flow-Based Biochips: Past Successes and Future Challenges," Proceedings of IEEE Annual Symposium on VLSI (ISVLSI-2018), pp., Hong Kong, July 2018.

  119. W. Ji, T.-Y. Ho, and H. Yao, "More Effective Randomly-Designed Microfluidics," Proceedings of IEEE Annual Symposium on VLSI (ISVLSI-2018), pp., Hong Kong, July 2018.

  120. C.-Y. Lin, J.-D. Huang, H. Yao, and T.-Y. Ho, "A Comprehensive Security System of Digital Microfluidic Biochips," Proceedings of IEEE International Test Conference in Asia (ITC-Asia-2018), pp., Harbin, China, August 2018.

  121. *P.-Y. Cheng, T. Kazuyoshi, and T.-Y. Ho, "Multi-Terminal Routing with Length-Matching for Rapid Single Flux Quantum Circuits," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2018), pp., San Diego, CA, November 2018.

  122. *Y. Zhu, B. Li, T.-Y. Ho, Q. Wang, H. Yao, R. Wille, and U. Schlichtmann, "Multi-Channel and Fault-Tolerant Control Multiplexing for Flow-Based Microfluidic Biochips," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2018), pp., San Diego, CA, November 2018.

  123. J.-D. Li, S.-J. Wang, S.-M. Li, and T.-Y. Ho, "Digital Rights Management for Paper-Based Microfluidic Biochips," Proceedings of IEEE Asian Test Symposium (ATS-2018), pp., Hefei, China, November 2018.

  124. T.-C. Liang, Y.-S. Chan, ­T.-Y. Ho, K. Chakrabarty, and C.-Y. Lee, "Sample Preparation for Multiple-Reactant Bioassays on Micro-Electrode-Dot-Array Biochips," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2019), pp., Tokyo, Japan, January 2019.

  125. S.-H. Lin and T.-Y. Ho, "Autonomous Vehicle Routing In Multiple Intersections," Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC-2019), pp., Tokyo, Japan, January 2019.

  126. Z. Chen, X. Huang, W. Guo, B. Li, T.-Y. Ho, and U. Schlichtmann, "Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2019), pp., Florence, Italy, March 2019.

  127. Y.-H. Lin, T.-Y. Ho, B. Li, and U. Schlichtmann, "Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2019), pp., Florence, Italy, March 2019. (Best Paper Nomination) 

  128. T.-W. Huang, Y.-Y. Tsai, C.-W. Lin, and T.-Y. Ho, "Vehicle Sequence Reordering with Cooperative Adaptive Cruise Control," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2019), pp., Florence, Italy, March 2019.

  129. Z. Zhou, S. Chahal, T.-Y. Ho, and A. Ivanov, "Supervised-Learning Congestion Predictor For Routability-Driven Global Routing", Proceedings of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT-2019), pp. 1-4, Hsinchu, Taiwan, April 2019.

  130. *X. Huang, T.-Y. Ho, W. Guo, B. Li, and U. Schlichtmann, "MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports," Proceedings of ACM/IEEE Design Automation Conference (DAC-2019), pp., Las Vegas, NV, June 2019.

  131. *G.-M. Lai, T.-W. Huang, and T.-Y. Ho, "A General Cache Framework for Efficient Generation of Timing Critical Paths," Proceedings of ACM/IEEE Design Automation Conference (DAC-2019), pp., Las Vegas, NV, June 2019.

  132. *M. Li, T.-M. Tseng, Y. Ma, T.-Y.i Ho, and Ulf Schlichtmann, "VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2019), pp., Westminster, CO, November 2019.

  133. *C.-J. Liang, X. Huang, T.-Y. Ho, J. Li, and C. Kim, "Open-Source Incubation Ecosystem for Digital Microfluidics — Status and Roadmap," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2019), pp., Westminster, CO, November 2019.

  134. *T.-M. Tseng, M. Li, T.-Y. Ho, and Ulf Schlichtmann, "Cloud Columba: Accessible Design Automation Platform for Production and Inspiration," Proceedings of IEEE/ACM International Conference on Computer- Aided Design (ICCAD-2019), pp., Westminster, CO, November 2019.

  135. Y. Zhu, L. Zhang, T. Wang, B. Li, Y. Shi, T.-Y. Ho, and U. Schlichtmann, "Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise," Proceedings of IEEE/ACM Design, Automation and Test in Europe (DATE-2020), pp., Grenoble, France, March 2020.

  136. T.-Y. Tsai, K. Yang, T.-Y. Ho, and Y. Jin, "Robust Adversarial Objects against Deep Learning Models," Proceedings of AAAI Conference on Artificial Intelligence, (AAAI-2020), pp., New York, US, February 2020.

  137. K. Yang, T.-Y. Tsai, H. Yu., T.-Y. Ho, and Y. Jin, "Beyond Digital Domain: Fooling Deep learning Based Recognition System in Physical World," Proceedings of AAAI Conference on Artificial Intelligence, (AAAI-2020), pp., New York, US, February 2020.

 

Other Conference Papers:

  1. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "A Fast Crosstalk-Driven Multilevel Routing System," The 14th VLSI Design/CAD Symposium, pp. 25-28, Hua-Lien, Taiwan, Aug. 2003.

  2. C.-F. Chang, T.-Y. Ho, and Y.-W. Chang, "XRoute: a multilevel routing system for the X-based architecture," The 16th VLSI Design/CAD Symposium, pp. 202-205, Hua-Lien, Taiwan, Aug. 2005.

  3. T.-W. Huang and T.-Y. Ho, "Contamination Aware Droplet Routing for Digital Microfluidic Biochips," Proceedings of International Workshop on Bio-Design Automation (IWBDA-2009), pp. 13, San Francisco, CA, July 2009.

  4. T.-W. Huang and T.-Y. Ho, " A Two-Stage ILP-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips," The 21th VLSI Design/CAD Symposium, pp. 407-410, Kao-Hsiung, Taiwan, Aug. 2010.

  5. P.-S. Wu and T.-Y. Ho, ''Bus-Driven Floorplanning with Bus Pin Alignment," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2010), pp. 308-313, Taipei, Taiwan, October 2010.

  6. T.-W. Huang and T.-Y. Ho, "Low-Power Broadcast Electrode-Addressing for Disposable Digital Microfluidic Biochips," Proceedings of International Workshop on Bio-Design Automation (IWBDA-2011), pp. 51-52, San Diego, CA, June 2011.

  7. T.-W. Huang, Y.-Y. Lin, J.-W. Chang, and T.-Y. Ho, "Chip-Level Design and Optimization for Digital Microfluidic Biochips," The 22th VLSI Design/CAD Symposium, pp. , Yun-Lin, Taiwan, Aug. 2011.

  8. S.-J. Jiang and T.-Y. Ho, "A Nonlinear Optimization Methodology for Resistor Matching in Analog Integrated Circuits," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2012), pp. 241-246, Beppu, Japan, March 2012.

  9. Z.-H. Yang and T.-Y. Ho, "Timing-Aware Clock Gating Algorithm for Pulse-Latch Circuits," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2012), pp. 445-450, Beppu, Japan, March 2012.

  10. T.-W. Huang and T.-Y. Ho, "Design Automation for Digital Microfluidic Biochips: From Fluidic-Level Toward Chip-Level," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2012), pp. 439-444, Beppu, Japan, March 2012. (Best Paper Award)

  11. S.-H. Yeh, J.-W. Chang, T.-W. Huang, and T.-Y. Ho, "Integrated Optimization for Digital Microfluidic Biochips Considering Fluidic-Chip Co-Design," The 23th VLSI Design/CAD Symposium, pp. , Ken-Ting, Taiwan, Aug. 2012.

  12. S. Bhattacharjee, A. Banerjee, T.-Y. Ho, K. Chakrabarty, and B. B. Bhattacharya, "Eco-Friendly Sample Preparation with Concentration Gradient on a Digital Microfluidic Biochip", Proceedings of International Conference on Eco-friendly Computing and Communication Systems (ICECCS), pp. Waknaghat, Himachal Pradesh, India, Oct. 2013. Lecture Notes in Computer Science (LNCS), Springer. (Best Paper Award)

  13. T.-M. Tseng, B. Li, T.-Y. Ho, Ulf Schlichtmann, "Iterative Refinement of Dense Meander Segments in High-speed Printed Circuit Boards", Proceedings of GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE-2013), Dresden, Germany, September 2013.

  14. T.-Y. Ho, "Physical Design for Microfluidic Biochips," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2013), pp. 290, Sapporo, Japan, October 2013. (Invited Talk)

  15. T.-Y. Ho, "Application of EDA Technologies to Non-EDA Areas," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2013), pp. 291, Sapporo, Japan, October 2013. (Invited Panelist)

  16. T.-Y. Huang, C.-J. Chang, C.-W. Lin, S. Roy, and T.-Y. Ho, "Intra-Vehicle Network Routing Algorithm for Weight and Wireless Transmit Power Minimization," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2015), pp. 72-77, Yilan, Taiwan, March 2015.

  17. Y. Shen, Q. Wang, H. Yao, T.-Y. Ho, and Y. Cai, "Contamination-Aware Routing Flow for Both Functional and Washing Droplets in Digital Microfluidic Biochips," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2015), pp. 350-355, Yilan, Taiwan, March 2015.

  18. Y.-W. Wu, S. Roy, Y. Shi, and T.-Y. Ho, "Obstacle-Avoiding Wind Turbine Placement for Power-Loss and Wake-Effect Optimization," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2015), pp. 356-361, Yilan, Taiwan, March 2015.

  19. J.-D. Li, S.-J. Wang, S.-M. Li, and T.-Y. Ho, "Test and Diagnosis of Paper-Based Microfluidic Biochips," Proceedings of VLSI Test Technology Workshop (VTTW-2015), pp., Tainan, Taiwan, July 2015.

  20. K. Chakrabarty, T.-Y. Ho, and R. Wille "Design of Microfluidic Biochips," Dagstuhl Report (Dagstuhl Seminar 15352), pp. 34-53, Dagstuhl, Germany, August 2015.

  21. B. Li, T.-M. Tseng, T.-Y. Ho, and U. Schlichtmann, "Design Automation for Microfluidic Biochips Considering Efficiency and Reliability," Proceedings of Mikrosystemtechnik Kongresses (MST-2015), pp., Karlsruhe, Germany, October 2015.

  22. C.-W. Hsien, C.-Y. Lin, Z. Li, and T.-Y. Ho, "IP Protection for Digital Microfluidic Biochips," The 27th VLSI Design/CAD Symposium, pp. , Kaohsiung, Taiwan, Aug. 2016.

  23. Q. Wang, H. Yao, T.-Y. Ho, and Y. Cai, "CORP: Control Routing for Paper-Based Digital Microfluidic Biochips," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2016), pp., Kyoto, Japan, October 2016.

  24. G.-R. Lu, T.-Y. Ho, and H.-M. Chen, "Multi-Level Droplet Routing in Active-Matrix Based Digital-Microfluidic Biochips," The 28th VLSI Design/CAD Symposium, pp. , Ken-Ting, Taiwan, Aug. 2017.

  25. C.Liu and T.-Y. Ho, "Test Vector Generation for Microfluidic Fully Programmable Valve Arrays (FPVAs)," Proceedings of Workshop on Synthesis and System Integration of Mixed Information technologies (SASIMI-2018), pp., Matsue, Japan, March 2018.

 

  Other Publications:

  1. S.-J. Chen and T.-Y. Ho, "A new interconnect architecture: X-architecture," Component Magazine, Jan. 2005 (Invited Article).

  2. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multi-Level Routing with Antenna Avoidance," Bulletin of the College of Engineering, NTU, No. 93, pp. 51-61, Feb. 2005.

  3. T.-Y. Ho, "Electron: An Efficient and Robust Droplet Routing Algorithm for Digital Microfluidic Biochips", Proceedings of Japan-Taiwan Semiconductor EDA Science and Technology Symposium, pp. 283-288, Kitakyushu, Japan, Sep. 2009.

  4. T.-W. Huang, C.-H. Lin, C.-H. Tsai, and T.-Y. Ho, "A Routability- and Performance-Driven Droplet Routing Simulator for Digital Microfluidic Biochips," Nano Communication, Vol. 17, No. 1, pp. 57-64, Mar. 2010 (Invited Paper).

  5. C.-L. Hsu, T.-W. Huang, J.-W. Chang, and T.-Y. Ho, "A Routability- and Performance-Driven Droplet Routing Simulator for Digital Microfluidic Biochips," Chemical Technology, Vol. 20, No. 6, pp. 130-143, Jun. 2012 (Invited Paper).

  6. T.-Y. Ho, "What is Digital Microfluidic Biochips?," ACM/SIGDA E-Newsletter, Vol. 43, No. 7, Jul. 2013 (Invited Article).

  7. S. Bhattacharjee, A. Banerjee, T.-Y. Ho, K. Chakrabarty, B. B. Bhattacharya: Algorithms for Producing Linear Dilution Gradient with Digital Microfluidics. arXiv, 2013.

  8. T.-Y. Ho, "Digital Microfluidic Biochips: Towards Hardware/Software Co-Design and Cyberphysical System Integration," Electrowetting, pp. 52, Jun. 2016.

 

Patent:

  1. T.-Y. Ho, S.-J. Jiang, and J.-L. Wu, Floorplanning Method for an Analog Integrated Circuit Layout, US Patent 8,726,214, May 13, 2014.

  2. T.-Y. Ho, S.-J. Jiang, and J.-L. Wu, Method of Resistor Matching in Analog Integrated Circuit Layout, US Patent 8,751,987, June 10, 2014.

  3. T.-C. Chen, P.-H. Wu, P.-H. Lin, and T.-Y. Ho, Knowledge-Based Analog Layout Generator, US Patent 9,256,706, February 9, 2016.