Port-Synchronizable Test sequence(cont II.)
- Definition : Port-Synchronizable test sequence
- Let T be a transition in a transition sequence E of
an FSM M. T is said to be port synchronizable for
(E,M), if the following two conditions hold:
- either PPI(T,E) is ƒÕ, or PPI(T,E) is not ƒÕ and the
input symbol of T is invalid for the head state of
any transition in PPI(T,E)
- If T is not a timeout transition, then head(T)
does not have a timeout transition.
-
- How to generate port-synchronizable
test sequence?
- No algorithm was proposed yet
Ref: K.Ctai and Y.C. Young ,¡¨Synchronizable Test sequence of
Finite State Machines,vol.30,issue:12, July1998