國立清華大學資訊工程學系
CS 4100 --- 計算機結構
91學年度上學期
Homework #4
(Due: 17:00PM, Nov. 22, 2002, in Room 734)
- In this exercise, you will write a verilog program to implementat a 4-bit ALU,
similar to that introduced in Chapter 4 of the textbook. The ALU will perform
add, sub, and, or. The input and output to the 4-bit
ALU are as follows.
Input: a and b are 4-bit quantities
Control line: c0 and c1 are the two
inputs to a 4-1 MUX. The 4-1 MUX decides which operation should be performed.
Output: R is a 4-bit quantity
The 4-bit ALU is similar to that shown in Figure 4.15 in P.235 of the textbook.
The 4-bit ALU consists of four 1-bit ALUs. Each 1-bit ALU is shown bellow.
[Program submission]: Submit your verilog program via email to TA.
In addiiotn, please turn in a page showing your input variables and output result.
Verilog使用說明:
先到 http://pads1.cs.nthu.edu.tw/~griffy/cs4100/veriwell/ 下載Veriwell的安裝檔和hw4.v（1-bit full adder verilog code and simulation code）
下載完之後，安裝Veriwell，裝完之後執行VeriLogger Pro，就會出現以下的圖：
接下來先選Editor去new一個HDL File，就會出現以下的圖：
編輯完後，選Project的Add HDL File把這個HDL File加入project中。
選Simulate的Build去compile，Run去跑出結果，就會出現以下的圖：
- You can modify the code and start from here!
- This code includes two modules, one module is 1-bit full adder, another
is the simulation about how to use 1-bit full adder and show the result.
- The circuit diagram of above 1-bit full adder.
