Po-Yuan Chen
pychen@cs.nthu.edu.tw
Department of Computer Science, National Tsing Hua University (NTHU)
101, Section 2 Kuang Fu Road, Hsinchu,Taiwan 30013, R.O.C.

Research Interests
Biography
Publications
Awards
Courses
My Links

Research Interests

Low Power Circuit Design, VLSI Synthesis, Hardware-software Codesign.

Biography

  • Ph.D.
  • in Computer Science, National Tsing Hua University (2009)
  • M.S.
  • in Computer Science, National Tsing Hua University (2004)
  • B.S.
  • in Computer Science, National Tsing Hua University (2002)

    Publications

    1. Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, and Hsi-Pin Ma, "Leakage Reduction, Delay Compensation Using Partition-based Tunable Body-Biasing Techniques ," accepted to be published in the ACM Transactions on Design, Automation of Electronic Systems (TODAES).
    2. Po-Yuan Chen, Kuan-Hsien Ho, and TingTing Hwang, "Skew Aware Polarity Assignment in Clock Tree ," accepted to be published in ACM Transactions on Design Automation of Electronic Systems (TODAES).
    3. Po-Yuan Chen, Che-Yu Liu, and TingTing Hwang, "Transition-Aware Decoupling-Capacitor Allocation in Power Noise Reduction ," in the 26th International Conference on Computer-Aided Design (ICCAD) , Nov. 2008.
    4. Wen-Wen Hsieh, Po-Yuan Chen, and TingTing Hwang, " A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design," IEEE Trans. on CAD of Integrated Circuits and Systems (TCAD) , 2007.
    5. Po-Yuan Chen, Kuan-Hsien Ho, and TingTing Hwang, "Skew Aware Polarity Assignment in Clock Tree ," in the 25th International Conference on Computer-Aided Design (ICCAD) , Nov. 2007.
    6. Wen-Wen Hsieh, Po-Yuan Chen, and TingTing Hwang, "Architecture Exploration: A Bus Architecture for Crosstalk Elimination in High Performance Processor Design ," in the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) , Oct. 2006.
    7. Yu-Hui Huang, Po-Yuan Chen, and TingTing Hwang, "Switching-Activity Driven Gate Sizing and Vth Assignment for Low Power Design," in the 11th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2006.
    8. Po-Yuan Chen, Tai-Yi Huang, and Ting-Shuo Chou, "An Optimal Balanced-Reward Scheduling Algorithm for Periodic Real-Time Tasks," in the 10th International Conference on Real-Time and Embedded Computing Systems and Applications (RTCSA), Aug. 2004.

    Experience

    1. 2008 台灣積體電路公司實習(2008 TSMC Intern)

    Awards

    1. 教育部九十一年度大專校院嵌入式軟體製作競賽佳作
    2. 2007思源EDA獎勵金
    3. 2008思源EDA獎勵金
    4. 教育部補助博士生赴國外研究(千里馬計畫)