Goal:

Contents:

  1. Introduction
  2. Why Hardware Description Languages?
  3. Anatomy of the Verilog (VHDL) HDL
  4. Modeling a Pipelined Processor
  5. Modeling System Blocks
  6. Modeling Cache Memories
  7. Modeling Asynchronous I/O: UART
  8. Verilog (VHDL) HDL for Synthesis
  9. Modeling a Floppy Disk Subsystem
  10. Useful Modeling and Debugging Techniques
  11. Term Project

Texts and References:

  1. Eli Sternheim, Rajvir Singh, Rajeev Madhavan, and Yatin Trivedi, "Digital Design with Verilog HDL," Automata Publishing Company, 1993.
  2. Eli Sternheim, Rajvir Singh, Rajeev Madhavan, and Yatin Trivedi, "Digital Design with VHDL HDL," Automata Publishing Company, 1993.
  3. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, and Eric S. Lin, "VHDL Modeling for Digital Design Synthesis," Kluwer Academic Publishers, 1995.
  4. Handouts