Benchmark Suite for Placement
Department of Computer Science
National Tsing Hua University
CAD/VLSI Laboratory, March 29, 2001
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Benchmark 1: addrgen Author: Stewart G. Smith Company: VLSI Vision Ltd. Format: Verilog Level: RTL Description: VPE Control and Line RAM Address Generator Top Module: addrgen I/O number: 96 Download: addrgen.v.gz (RTL) addrgen_syn.v.gz (Gate) |
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Benchmark 2: rgb_intr Author: Stewart G. Smith Company: VLSI Vision Ltd. Format: Verilog Level: RTL Description: RGB Interploation Top Module: rgb_interp I/O number: 71 Download: rgb_interp.v.gz (RTL) rgb_interp_syn.v.gz (Gate) |
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Benchmark 3: matrix Author: Stewart G. Smith Company: VLSI Vision Ltd. Format: Verilog Level: RTL Description: RGB matrix & Ap_cor Top Module: matrix I/O number: 119 Download: matrix.v.gz (RTL) matrix_syn.v.gz (Gate) |
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Benchmark 4: sdram_rdr Author: Vincent H. J. Chiou Company: CAD Lab, Dept. of CS, National Tsing Hua University Format: Verilog Level: RTL Description: SDRAM Controller Top Module: SDRAM_CON (main.v) I/O number: 95 Download: sdram.tar.gz (RTL) sdram_syn.v.gz (Gate) |
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Benchmark 5: 32bMAC Author: Yuan-Ming Liu Company: CAD Lab, Dept. of CS, National Tsing Hua University Format: Verilog Level: RTL Description: 32-bit MAC Top Module: MacUnit I/O number: 213 Download: MAC1.v.gz (RTL) MAC1_syn.v.gz (Gate) |
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Benchmark 6: 64bMAC Author: Yuan-Ming Liu Company: CAD Lab, Dept. of CS, National Tsing Hua University Format: Verilog Level: RTL Description: 64-bit MAC Top Module: MacUnit I/O number: 417 Download: MAC2.v.gz (RTL) MAC2_syn.v.gz (Gate) |
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Benchmark 7: VP2 Author: Stewart G. Smith Company: VLSI Vision Ltd. Format: Verilog Level: RTL Description: Video Processor (Engine) Top Module: main (main.v) I/O number: 323 Download: VP2.tar.gz (RTL) VP2_syn.v.gz (Gate) |