I will say of the Lord,
"He is my refuge and my fortress, my God,
in whom I trust." Psalm 91:2

Wai-Kei Mak
Associate Professor
Department of Computer Science
National Tsing Hua University
101 Kuan Fu Rd. Sec. 2
Hsinchu
Taiwan 300 R.O.C.
wkmak[at]cs.nthu.edu.tw
886-3-573-1209

Teaching

• FPGA Architecture and CAD

• Introduction to Computer-Aided Design of Integrated Circuits
• Computer Architecture
• Logic Design
• Hardware Lab

Research

My research interests are in computer-aided design of VLSI circuits, and combinatorial optimization.

Students interested in joining my lab may look here. Link to My Research Lab

Publications

• M.Y. Chan, F. Chin, C.N. Chu, and W.K. Mak, "Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes", Journal of Parallel and Distributed Computing, 33(1), pp.98-106, 1996.
• W.K. Mak and D.F. Wong, "On Optimal Board-Level Routing for FPGA-based Logic Emulation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16(3), pp.282-289, March 1997.
• W.K. Mak and D.F. Wong, "Board-Level Multi-Terminal Net Routing for FPGA-based Logic Emulation", ACM Transactions on Design Automation of Electronic Systems, vol.2(2), pp.151-167, April 1997.
• W.K. Mak and D.F. Wong, "Minimum Replication Min-Cut Partitioning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16(10), pp.1221-1227, Oct. 1997.
• W.K. Mak, D. Morton, and K. Wood, "Monte Carlo Bounding Techniques for Determining Solution Quality in Stochastic Programs", Operations Research Letters, vol.24(1-2), pp.47-56, Feb. 1999.
• W.K. Mak and D.F. Wong, "A Fast Hypergraph Min-Cut Algorithm for Circuit Partitioning", Integration, The VLSI Journal, vol.30(1), pp.1-11, Nov. 2000.
• W.K. Mak, "Min-Cut Partitioning with Functional Replication for Technology Mapped Circuits using Minimum Area Overhead", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.21(4), pp.491-497, April 2002.
• W.K. Mak and E.F.Y. Young, "Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.22(7), pp.952-959, July 2003.
• H. Li, W.K. Mak, and S. Katkoori, "Power Minimization Algorithms for LUT-based FPGA Technology Mapping", ACM Transactions on Design Automation of Electronic Systems, vol.9(1), pp.33-51, Jan. 2004.
• W.K. Mak, "I/O Placement for FPGAs with Multiple I/O Standards", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.23(2), pp.315-320, Feb. 2004.
• W.K. Mak and C.L. Lai, "On Constrained Pin Mapping for FPGA-PCB Co-Design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25(11), pp.2393-2401, Nov. 2006.
• W.C. Chao and W.K.Mak, "Low Power Gated and Buffered Clock Network Construction", ACM Transactions on Design Automation of Electronic Systems, vol.13(1), pp.20.1-20.20, Jan. 2008.

• M.Y. Chan, F. Chin, C.N. Chu, and W.K. Mak, "Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes", in Proceedings of IEEE Symposium on Parallel and Distributed Processing, pp.285-289, 1993.
• W.K. Mak and D.F. Wong, "On Optimal Board-Level Routing for FPGA-based Logic Emulation", in Proceedings of ACM/IEEE Design Automation Conference , pp.552-556, 1995.
• W.K. Mak and D.F. Wong, "Board-Level Multi-Terminal Net Routing for FPGA-based Logic Emulation", in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp.339-344, 1995.
• W.K. Mak and D.F. Wong, "Minimum Replication Min-Cut Partitioning", in Proceedings of IEEE/ACM Internation Conference on Computer-Aided Design , pp.205-210, 1996.
• W.K. Mak and D.F. Wong, "Channel Segmentation Design for Symmetrical FPGAs", in Proceedings of IEEE International Conference on Computer Design , pp.496-501, 1997.
• W.K. Mak and D.F. Wong, "Performance-Driven Board-Level Routing for FPGA-based Logic Emulation", in Proceedings of IEEE International Conference on Computer Design, pp.199-201, 1998.
• W.K. Mak and D.F. Wong, "A Fast Hypergraph Minimum Cut Algorithm", in Proceedings of IEEE International Symposium on Circuits and Systems, pp.VI170-173, 1999. (Invited paper)
• H.M. Chen, D.F. Wong, W.K. Mak, and H.H. Yang, "Faster and More Accurate Wiring Evaluation in Interconnect-Centric Floorplanning", in Proceedings of ACM Great Lakes Symposium on VLSI, pp.62-67, 2001.
• H. Li, W.K. Mak, and S. Katkoori, "LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth", in Proceedings of IEEE-CS Workshop on VLSI, pp.123-128, 2001.
• W.K. Mak, "Min-Cut Partitioning with Functional Replication for Technology Mapped Circuits using Minimum Area Overhead", in Proceedings of ACM International Symposium on Physical Design, pp.100-105, 2001.
• W.K. Mak and E.F.Y. Young, "Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning", in Proceedings of ACM International Symposium on Physical Design, pp.190-195, 2002.
• H. Li, W.K. Mak, and S. Katkoori, "Efficient LUT-Based FPGA Technology Mapping for Power Minimization", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.353-358, 2003. (Best paper nomination)
• W.K. Mak, "I/O Placement for FPGA with Multiple I/O Standards", in Proceedings of ACM International Symposium on Field-Programmable Gate Arrays, pp.51-57, 2003.
• E.S.H. Wong, E.F.Y. Young, and W.K. Mak, "Clustering Based Acyclic Multi-way Partitioning", in Proceedings of ACM Great Lakes Symposium on VLSI, pp.203-206, 2003.
• H. Li, W.K. Mak, and S. Katkoori, "Force-Directed Performance-Driven Placement Algorithm for FPGAs", in Proceedings of IEEE-CS Annual Symposium on VLSI, pp.193-198, 2004.
• W.K. Mak, "Modern FPGA Constrained Placement", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.779-784, 2005.
• W.K. Mak, "Faster Min-Cut Computation in Unweighted Hypergraphs/Circuit Netlists", in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test, pp.67-70, 2005.
• W.K. Mak and H. Li, "Placement for Modern FPGAs", in Proceedings of Emerging Information Technology Conference, 2005. (Invited paper)
• C.C. Chen and W.K. Mak, "A Multi-Technology-Process Reticle Floorplanner and Wafer Dicing Planner for Multi-Project Wafers", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.777-782, 2006.
• W.K. Mak and J.W. Chen, "Voltage Island Generation under Performance Requirement for SoC Designs", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.798-803, 2007.
• C.H. Wang and W.K. Mak, "Lamda-Geometry Clock Tree Construction with Wirelength and Via Minimization", in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test, pp.124-127, 2007.
• Y.R. He and W.K.Mak, "Optimal Buffering of FPGA Interconnect for Expected Delay Optimization", in Proceedings of International Conference on Field Programmable Technology, pp.289-292, 2007.
• Y.J. Ho and W.K.Mak, "Power and Density-Aware Buffer Insertion", in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test, pp.287-290, 2008.
• C.Y. Wang and W.K. Mak, "Signal Skew Aware Floorplanning and Bumper Signal Assignment Technique for Flip-Chip", Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.341-346, 2009.
• C.Y. Chuang and W.K. Mak, "Accurate Closed-form Parameterized Block-based Statistical Timing Analysis Applying Skew-Normal Distribution", Proceedings of International Symposium on Quality Electronic Design, pp.68-73, 2009.

• W.K. Mak, "The Design of a Graduate FPGA Design and Design Automation Courese", in Proceedings of the European Workshop on Microelectronics Education, pp.167-169, 2002.