I will say of the Lord,
"He is my refuge and my fortress, my God,
in whom I trust." Psalm 91:2

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麥偉基 Wai-Kei Mak
Professor
Department of Computer Science
National Tsing Hua University
101 Kuan Fu Rd. Sec. 2
Hsinchu
Taiwan 300 R.O.C.
wkmak[at]cs.nthu.edu.tw

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Teaching

Graduate Courses

• VLSI Design for Manufacturability
• FPGA Architecture and CAD

Undergradate Courses

• Discrete Mathematics
• Logic Design
• Introduction to Computer-Aided Design of Integrated Circuits
• Computer Architecture
• Hardware Lab

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Research

My research interests are in computer-aided design of VLSI circuits and systems, and combinatorial optimization.

Students interested in joining my lab may check the Link to My Research Lab

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Awards & Honors

• 優等: 2023國際積體電路電腦輔助設計(CAD)軟體製作競賽 定題組
• Best Paper Award Nomination: 2018 ACM International Symposium on Physical Design (ISPD) for the paper “Pin Assignment Optimization for Multi-FPGA Systems”.
• Best Paper Award Nomination: 2017 ACM International Symposium on Physical Design (ISPD) for the paper “Pin Accessibility-Driven Detailed Placement Refinement”.
• Best Paper Award Recipient: 2014 IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) for the paper “Flexible Packed Stencil Design with Multiple Shaping Apertures for E-Beam Lithography”.
• Best Paper Award nomination: 2010 ACM International Symposium on Physical Design (ISPD) for the paper “FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction”.
• Best Paper Award nomination: 2010 ACM International Symposium on Physical Design (ISPD) for the paper “SafeChoice: A Novel Clustering Algorithm for Wirelength-Driven Placement”.
• Best Paper Award nomination: 2003 IEEE Asia and South Pacific Design Automation Conference for the paper “Efficient LUT-Based FPGA Technology Mapping for Power Minimization”.
• 2nd Place: TAU 2013 Variation Aware Timing Analysis Contest
• 3rd Place: IEEE CEDA 2011 PATMOS Timing Analysis Contest
• 1st Place: 2008 International Conference on Field Programmable Technology Design Contest
• 特優: 教育部99學年度大學校院積體電路電腦輔助設計軟體製作競賽定題組
• 優等: 教育部98學年度大學校院積體電路電腦輔助設計軟體製作競賽馬拉松組
• 佳作: 教育部93學年度大學校院積體電路設計競賽FPGA組
• 佳作: 教育部92學年度大學校院積體電路電腦輔助設計軟體製作競賽定題組
• 國立清華大學2006年新進人員研究獎
• 國立清華大學電機資訊學院94學年度新進人員研究獎
• Invited Presentation: Invited session on graph theory and its application in VLSI CAD at the 50th IEEE International Symposium on Circuits and Systems, 1999.
• Selection by the Argonne National Laboratory of the U.S. Department of Energy for inclusion in its NEOS Server, 2000, for research work on stochastic linear optimization.

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Professional Services

• Guest Editor: Journal of VLSI Signal Processing Systems
• General Chair: 2008 International Conference on Field-Programmable Technology
• TPC Chair: 2006 International Conference on Field-Programmable Technology
• TPC Vice-Chair: 2022 IEEE Asia South Pacific Design Automation Conference
• Publication Chair: 2010 IEEE Asia South Pacific Design Automation Conference; 2006 VLSI Design/CAD Symposium, Taiwan R.O.C.
• TPC Members: International Conference on Computer Aided Design (2020-2023), Design Automation Conference (2019), IEEE Asia South Pacific Design Automation Conference (2005, 2008-2009, 2011, 2016-2017), International Conference on Field Programmable Logic and Applications (2007-present), International Conference on Field-Programmable Technology (2006-2011)
• Steering Committee: International Conference on Field-Programmable Technology (2009-present)
• Session Chair: IEEE Asia South Pacific Design Automation Conference (2005), International Conference on Field-Programmable Technology (2007), VLSI Design/CAD Symposium, Taiwan R.O.C (2004, 2013).
• International Education Forum Reviewer, ACM Special Interest Group on Design Automation PhD Forum at Design Automation Conference, 2002.
• 國科會工程處「前瞻晶片設計軟體技術開發計畫」共同召集人
• 第33屆超大型積體電腦設計暨計算機輔助設計技術研討會(VLSI Design/CAD Symposium) 議程主席
• 教育部顧問室EDA聯盟94年度CAD產學合作座談會協同主辦人
• 教育部顧問室DAT聯盟95、96、97年度CAD產學合作座談會主辦人

Publications

Journal Papers

• M.Y. Chan, F. Chin, C.N. Chu, and W.K. Mak, "Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes", Journal of Parallel and Distributed Computing, 33(1), pp.98-106, 1996.
• W.K. Mak and D.F. Wong, "On Optimal Board-Level Routing for FPGA-based Logic Emulation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16(3), pp.282-289, March 1997.
• W.K. Mak and D.F. Wong, "Board-Level Multi-Terminal Net Routing for FPGA-based Logic Emulation", ACM Transactions on Design Automation of Electronic Systems, vol.2(2), pp.151-167, April 1997.
• W.K. Mak and D.F. Wong, "Minimum Replication Min-Cut Partitioning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16(10), pp.1221-1227, Oct. 1997.
• W.K. Mak, D. Morton, and K. Wood, "Monte Carlo Bounding Techniques for Determining Solution Quality in Stochastic Programs", Operations Research Letters, vol.24(1-2), pp.47-56, Feb. 1999.
• W.K. Mak and D.F. Wong, "A Fast Hypergraph Min-Cut Algorithm for Circuit Partitioning", Integration, The VLSI Journal, vol.30(1), pp.1-11, Nov. 2000.
• W.K. Mak, "Min-Cut Partitioning with Functional Replication for Technology Mapped Circuits using Minimum Area Overhead", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.21(4), pp.491-497, April 2002.
• W.K. Mak and E.F.Y. Young, "Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.22(7), pp.952-959, July 2003.
• H. Li, W.K. Mak, and S. Katkoori, "Power Minimization Algorithms for LUT-based FPGA Technology Mapping", ACM Transactions on Design Automation of Electronic Systems, vol.9(1), pp.33-51, Jan. 2004.
• W.K. Mak, "I/O Placement for FPGAs with Multiple I/O Standards", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.23(2), pp.315-320, Feb. 2004.
• W.K. Mak and C.L. Lai, "On Constrained Pin Mapping for FPGA-PCB Co-Design", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25(11), pp.2393-2401, Nov. 2006.
• W.C. Chao and W.K.Mak, "Low Power Gated and Buffered Clock Network Construction", ACM Transactions on Design Automation of Electronic Systems, vol.13(1), pp.20.1-20.20, Jan. 2008.
• G. Ajwani, C. Chu, and W.K. Mak, "FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.30(2), pp.194-204, Feb. 2011.
• J.Z. Yan, C. Chu, and W.K. Mak, "SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.30(7), pp.1020-1033, July 2011.
• S.H. Wang, Y.Y. Liang, T.Y. Kuo, and W.K. Mak, "Power-Driven Flip-Flop Merging and Relocation", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31(2), pp.180-191, Feb. 2012.
• Y.Y. Liang, T.Y. Kuo, S.H. Wang, and W.K. Mak, “ALMmap: Technology Mapping for FPGAs with Adaptive Logic Modules”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31(7), pp.1134-1139, July 2012.
• W.K. Mak, Y.C. Lin, C. Chu, and T.C. Wang, “Pad Assignment for Die-Stacking System-in-Package Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31(11), pp.1711-1722, Nov. 2012.
• W.K. Mak and C. Chu, “Rethinking the Wirelength Benefit of 3D Integration”, IEEE Transactions on Very Large Scale Integration Systems, vol.20(12), pp.2346-2351, Dec. 2012.
• C.R. Li, W.K. Mak, and T.C. Wang, “Fast Fixed-Outline 3-D IC Floorplanning with TSV Co-placement”, IEEE Transactions on Very Large Scale Integration Systems, vol.21(3), pp.523-532, March 2013.
• F.Y. Chang, R.S. Tsay, W.K. Mak, and S.H. Chen, “MANA: A Shortest Path MAze Algorithm under Separation and Minimum Length NAnometer Rules”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.32(10), pp.1557-1568, Oct. 2013.
• S.I. Lei and W.K. Mak, “Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.32(12), pp.1866-1878, Dec. 2013.
• W.K. Mak and C. Chu, “E-Beam Lithography Character and Stencil Co-Optimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.33(5), pp.741-751, May 2014.
• C. Chu and W.K. Mak, “Flexible Packed Stencil Design with Multiple Shaping Apertures and Overlapping Shots for E-Beam Lithography”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.34(10), pp.1652-1663, Oct. 2015.
• J.H. Chang, H.I. Wu, H.L. Pai, R.S. Tsay, and W.K. Mak, “Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.34(11), pp.1822-1835, Nov. 2015.
• S.I. Lei and W.K. Mak, “Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.35(2), pp.246-259, Feb. 2016.
• P.Y. Wu, W.K. Mak, T.C. Wang, C. Zhuo, K. Unda, and Y. Shi, “A routing framework for technology migration with bump encroachment”, Integration, the VLSI Journal, vol.58, pp.1-8, June 2017.
• W.K. Mak, W.S. Kuo, S.H. Zhang, S.I. Lei, and C. Chu, “Minimum Implant Area-Aware Placement and Threshold Voltage Refinement”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.36(7), pp.1103-1112, July 2017.
• Y. Ding, C. Chu, and W.K. Mak, “Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.36(8), pp.1381-1394, Aug. 2017.
• Y. Ding, C. Chu, and W.K. Mak, “Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.37(3), pp.657-668, Mar. 2018.
• Y.C. Liao and W.K. Mak, “Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems with Time-Multiplexed I/Os”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.40(3), pp.494-506, Mar. 2021.
• C.C. Wang and W.K. Mak, “A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum Logic Circuits with Maximum Path Length Consideration”, IEEE Transactions on Applied Superconductivity, vol.32(5), Aug. 2022.
• Y.J. Xie and W.K. Mak, “Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.42(4), pp.1255-1267, April 2023.

Conference Papers

• M.Y. Chan, F. Chin, C.N. Chu, and W.K. Mak, "Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes", in Proceedings of IEEE Symposium on Parallel and Distributed Processing, pp.285-289, 1993.
• W.K. Mak and D.F. Wong, "On Optimal Board-Level Routing for FPGA-based Logic Emulation", in Proceedings of ACM/IEEE Design Automation Conference , pp.552-556, 1995.
• W.K. Mak and D.F. Wong, "Board-Level Multi-Terminal Net Routing for FPGA-based Logic Emulation", in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp.339-344, 1995.
• W.K. Mak and D.F. Wong, "Minimum Replication Min-Cut Partitioning", in Proceedings of IEEE/ACM International Conference on Computer-Aided Design , pp.205-210, 1996.
• W.K. Mak and D.F. Wong, "Channel Segmentation Design for Symmetrical FPGAs", in Proceedings of IEEE International Conference on Computer Design , pp.496-501, 1997.
• W.K. Mak and D.F. Wong, "Performance-Driven Board-Level Routing for FPGA-based Logic Emulation", in Proceedings of IEEE International Conference on Computer Design, pp.199-201, 1998.
• W.K. Mak and D.F. Wong, "A Fast Hypergraph Minimum Cut Algorithm", in Proceedings of IEEE International Symposium on Circuits and Systems, pp.VI170-173, 1999. (Invited paper)
• H.M. Chen, D.F. Wong, W.K. Mak, and H.H. Yang, "Faster and More Accurate Wiring Evaluation in Interconnect-Centric Floorplanning", in Proceedings of ACM Great Lakes Symposium on VLSI, pp.62-67, 2001.
• H. Li, W.K. Mak, and S. Katkoori, "LUT-Based FPGA Technology Mapping for Power Minimization with Optimal Depth", in Proceedings of IEEE-CS Workshop on VLSI, pp.123-128, 2001.
• W.K. Mak, "Min-Cut Partitioning with Functional Replication for Technology Mapped Circuits using Minimum Area Overhead", in Proceedings of ACM International Symposium on Physical Design, pp.100-105, 2001.
• W.K. Mak and E.F.Y. Young, "Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning", in Proceedings of ACM International Symposium on Physical Design, pp.190-195, 2002.
• H. Li, W.K. Mak, and S. Katkoori, "Efficient LUT-Based FPGA Technology Mapping for Power Minimization", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.353-358, 2003. (Best paper nomination)
• W.K. Mak, "I/O Placement for FPGA with Multiple I/O Standards", in Proceedings of ACM International Symposium on Field-Programmable Gate Arrays, pp.51-57, 2003.
• E.S.H. Wong, E.F.Y. Young, and W.K. Mak, "Clustering Based Acyclic Multi-way Partitioning", in Proceedings of ACM Great Lakes Symposium on VLSI, pp.203-206, 2003.
• H. Li, W.K. Mak, and S. Katkoori, "Force-Directed Performance-Driven Placement Algorithm for FPGAs", in Proceedings of IEEE-CS Annual Symposium on VLSI, pp.193-198, 2004.
• W.K. Mak, "Modern FPGA Constrained Placement", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.779-784, 2005.
• W.K. Mak, "Faster Min-Cut Computation in Unweighted Hypergraphs/Circuit Netlists", in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test, pp.67-70, 2005.
• W.K. Mak and H. Li, "Placement for Modern FPGAs", in Proceedings of Emerging Information Technology Conference, 2005. (Invited paper)
• C.C. Chen and W.K. Mak, "A Multi-Technology-Process Reticle Floorplanner and Wafer Dicing Planner for Multi-Project Wafers", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.777-782, 2006.
• W.K. Mak and J.W. Chen, "Voltage Island Generation under Performance Requirement for SoC Designs", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.798-803, 2007.
• C.H. Wang and W.K. Mak, "Lamda-Geometry Clock Tree Construction with Wirelength and Via Minimization", in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test, pp.124-127, 2007.
• Y.R. He and W.K.Mak, "Optimal Buffering of FPGA Interconnect for Expected Delay Optimization", in Proceedings of International Conference on Field Programmable Technology, pp.289-292, 2007.
• Y.J. Ho and W.K.Mak, "Power and Density-Aware Buffer Insertion", in Proceedings of IEEE International Symposium on VLSI Design, Automation & Test, pp.287-290, 2008.
• C.Y. Wang and W.K. Mak, "Signal Skew Aware Floorplanning and Bumper Signal Assignment Technique for Flip-Chip", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.341-346, 2009.
• C.Y. Chuang and W.K. Mak, "Accurate Closed-form Parameterized Block-based Statistical Timing Analysis Applying Skew-Normal Distribution", Proceedings of International Symposium on Quality Electronic Design, pp.68-73, 2009.
• Y.C. Lin, W.K. Mak, C. Chu, and T.C. Wang, "Pad-Assignment for Die-Stacking System-in-Package Design", in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp.249-255, 2009.
• F.Y. Chang, R.S. Tsay, and W.K. Mak, "How to Consider Shorts and Guarantee Yield Rate Improvement for Redundant Wire Insertion", in Proceedings of International IEEE/ACM Confernece on Computer-Aided Design, pp.33-38, 2009.
• G. Ajwani, C. Chu, and W.K. Mak, "FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction", in Proceedings of ACM International Symposium on Physical Design, pp.27-34, 2010. (Best paper nomination)
• J.Z.Yan, C. Chu, and W.K. Mak, "SafeChoice: A Novel Clustering Algorithm for Wirelength-Driven Placement", in Proceedings of ACM International Symposium on Physical Design, pp.185-192, 2010. (Best paper nomination)
• D.Y. Liu, W.K. Mak, and T.C. Wang, "Temperature-Constrained Fixed-Outline Floorplanning for Die-Stacking System-in-Package Design", in Proccedings of ACM Great Lakes Symposium on VLSI, pp.423-428, 2010.
• F.Y. Chang, R.S. Tsay, W.K. Mak, and S.H. Chen, "Cut-Demand Based Routing Resource Allocation and Consolidation for Routability Enhancement", in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.533-538, 2011.
• S.H. Wang, Y.Y. Liang, T.Y. Kuo, and W.K. Mak, "Power-Driven Flip-Flop Merging and Relocation", in Proceedings of ACM International Symposium on Physical Design, pp.107-114, 2011.
• S.I. Lei and W.K.Mak, "Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign", in Proceedings of Field Programmable Logic and Applications, pp.435-440, 2011.
• T.Y. Kuo, Y.Y. Liang, S.H. Wang, and W.K. Mak, “Experiences of Designing a STA Engine in the PATMOS STA Contest”, in Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2012. (invited paper)
• C.Y. Hong, W.K. Mak, and T.C. Wang, “Temperature-Constrained Fixed-Outline Floorplanning for 3D ICs”, in Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), pp. 457-459, 2012.
• F.Y. Chang, R.S. Tsay, W.K. Mak, and S.H. Chen, “A Separation and Minimum Wire Length Constrained Maze Routing Algorithm under Nanometer Wiring Rules”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.175-180, 2013.
• C. Chu and W.K. Mak, “Flexible Packed Stencil Design with Multiple Shaping Apertures for E-Beam Lithography”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.137-142, 2014. (Best Paper Award, 1 out of 343 submissions)
• S.K. Wu, P.Y. Hsu, and W.K. Mak, “A Novel Wirelength-Driven Packing Algorithm for FPGAs with Adaptive Logic Modules”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.501-506, 2014.
• S.I. Lei, C. Chu, and W.K. Mak, “Double Patterning-Aware Detailed Routing with Mask Usage Balancing”, in Proceedings of International Symposium on Quality Electronic Design, pp.219-223, 2014.
• Y. Ding, C. Chu, and W.K. Mak, “Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout”, in Proceedings of Design Automation Conference, 2014.
• C.H. Tsai and W.K. Mak, “A Fast Parallel Approach for Common Path Pessimism Removal”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.372-377, 2015.
• Y. Ding, C. Chu, and W.K. Mak, “Detailed Routing for Space-Is-Metal Type Self-Aligned Double/Quadruple Patterning Lithography”, in Proceedings of Design Automation Conference, 2015.
• S.I. Lei, W.K. Mak, and C. Chu, “Minimum Implant Area-Aware Placement and Threshold Voltage Refinement”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.192-197, 2016.
• Y. Ding, C. Chu, and W.K. Mak, “Self-Aligned Double Patterning-Aware Detailed Routing with Double Via Insertion and Via Manufacturability Consideration”, in Proceedings of Design Automation Conference, 2016.
• C.Y. Hung, P.Y. Chou, and W.K. Mak, “Optimizing DSA-MP Decomposition and Redundant Via Insertion with Dummy Vias”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, pp.378-383, 2017.
• Y. Ding, C. Chu, and W.K. Mak, “Pin Accessibility-Driven Detailed Placement Refinement”, in Proceedings of ACM International Symposium on Physical Design, pp.133-140, 2017. (Best paper nomination)
• C.Y. Hung, P.Y. Chou, and W.K. Mak, “Mixed-Cell-Height Standard Cell Placement Legalization”, in Proceedings of ACM Great Lakes Symposium on VLSI, pp.149-154, 2017.
• L. Feng, Y. Wang, J. Hu, W.K. Mak, and J. Rajendran, “Making Split Fabrication Synergistically Secure and Manufacturable”, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2017.
• W.S. Kuo, S.H. Zhang, W.K. Mak, R. Sun, and Y.K. Leow, “Pin Assignment Optimization for Multi-2.5D FPGA-based Systems”, in Proceedings of ACM International Symposium on Physical Design, pp. 106-113, 2018. (Best paper nomination)
• Y.H. Cheng, D.W. Huang, W.K. Mak, and T.C. Wang, “A Practical Detailed Placement Algorithm under Multi-Cell Spacing Constraints”, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2018.
• Y.J. Xie, K.Y. Chen, and W.K. Mak, “Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, 2021.
• B.Y. Chen, C.C. Fang, W.K. Mak, and T.C. Wang, “Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs”, in Proceedings of ACM International Symposium on Physical Design, 2021.
• C.C. Wang and W.K. Mak, “A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits”, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2021.
• K.Y. Chen, H.C. Hsu, W.K. Mak, and T.C. Wang, “HybridGP: Global Placement for Hybrid-Row-Height Designs”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, 2022.
• C.H. Wu, W.K. Mak, and C. Chu, “Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement”, in Proceedings of ACM International Symposium on Physical Design, 2022.
• M.Y. Liu, Y.C. Lai, W.K. Mak, and T.C. Wang, “Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization”, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2022.
• C.Y. Huang, C.H. Lien, and W.K. Mak, “Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem”, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, 2022.
• S.H. Liang, T.L. Hsiung, W.K. Mak, and T.C. Wang, “Hybrid-Row-Height Design Placement Legalization Considering Cell Variants”, in Proceedings of ACM Great Lakes Symposium on VLSI, 2023.
• C.Y. Huang and W.K. Mak, “Row Planning and Placement for Hybrid-Row-Height Designs”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, 2024.
• T.C. Lin, F.Y. Hsu, W.K. Mak, and and T.C. Wang, “An Effective Netlist Planning Approach for Double-sided Signal Routing”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, 2024.
• C.Y. Huang and W.K. Mak, “CTQr: Control and Timing-Aware Qubit Routing”, in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference, 2024.
• B.H. Wu and W.K. Mak, “Optimization for Buffer and Splitter Insertion in AQFP Circuits with Local and Group Movement”, in Proceedings of ACM International Symposium on Physical Design, 2024.

Education Paper

• W.K. Mak, "The Design of a Graduate FPGA Design and Design Automation Courese", in Proceedings of the European Workshop on Microelectronics Education, pp.167-169, 2002.

Patents

• W.K. Mak and W.C. Chao, “Method for Reducing Power Consumption of Integrated Circuit”, U.S. Patent 7917880
• F.Y. Chang, W.K. Mak, and R.S. Tsay, “Method for Improving Yield Rate Using Redundant Wire Insertion”, U.S. Patent 8336001.
• F.Y. Chang, S.H. Chen, T.C. Chen, R.S. Tsay, and W.K. Mak, “Systems and Methods for Designing and Making Integrated Circuits with Consideration of Wiring Demand Ratio”, U.S. Patent 8407647.
• F.Y. Chang, S.H. Chen, T.C. Chen, R.S. Tsay, and W.K. Mak, “Systems and Methods for Designing Integrated Circuits with Consideration of Horizontal and Vertical Wiring Demand Ratios”, U.S. Patent 9665679.
• F.Y. Chang, S.H. Chen, R.S. Tsay, and W.K. Mak, “Separation and Minimum Wire Length Constrained Maze Routing Method and System”, U.S. Patent 10192019.
• B.Y. Chen, C.C. Fang, W.K. Mak, and T.C. Wang, “Method, System, and Storage Medium for Resolving Coloring Conflict in Multi-patterning Lithography”, U.S. Patent 10474038.
• M.K. Hsu, S.H. Chen, W.K. Mak, T.C. Wang, Y.H. Cheng, D.H. Huang, “Method and system of revising a layout diagram”, U.S. Patent 10776551.
• M.K. Hsu, S.H. Chen, W.K. Mak, T.C. Wang, Y.H. Cheng, D.H. Huang, “Method and system of generating a layout diagram”, U.S. Patent 11062076.
• M.K. Hsu, S.H. Chen, W.K. Mak, T.C. Wang, Y.H. Cheng, D.H. Huang, “Method and system of generating a layout diagram”, U.S. Patent 11741286.