Prof. TingTing Hwang's Publications


A. Journal Papers
  1. Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang, "A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements.," to appear in IEEE Transactions on Very Large Scale Integration Systems. Vol. PP, Issue 99, pp. 1-13, 2016.
  2. Wei-Hen Lo, Kang Chi, and TingTing Hwang, "Architecture of Ring-Based Redundant TSV for Clustered Faults.," to appear in IEEE Transactions on Very Large Scale Integration Systems. Vol. 24, Issue 12, pp. 3437-3449, 2016.
  3. F. W. Chen, and TingTing Hwang, "Clock Tree Synthesis with Methodology of Re-Use in 3-D IC.," to appear in ACM Journal on Emerging Technologies in Computing Systems. Vol. 10, Issue 3, pp. 22, 2014.
  4. P. Y. Hsu, H. T. Chen and TingTing Hwang, " Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC," to appear in IEEE Transactions on CAD of Integrated Circuits and Systems Vol. 33, Issue 7, pp. 1031-1042, 2014.
  5. W. H. Lo, A. C. Hsieh and TingTing Hwang, " Utilizing Circuit Structure for Scan Chain Diagnosis," to appear in IEEE Transactions on VLSI Systems Vol. 22, Issue 12, pp. 2766-2778, 2014.
  6. Ang-Chih Hsieh and TingTing Hwang, "Thermal-Aware Memory Mapping in 3D Designs," to appear in ACM Transactions on Embedded Computing Systems Vol 13, Issue 1, pp. 4, 2013.
  7. F. W. Chen, Shih-Liang Chen, Yung-Sheng Lin and TingTing Hwang, "A Physical-Location Aware X-bit Redistribution for Maximum IR-Drop Reduction," to appear in IEEE Transactions on VLSI Systems Vol. 29, Issue12, pp. 2046-2050, 2010.
  8. Ang-Chih Hsieh and TingTing Hwang, "Run-Time Reconfiguration of Expandable Cache for Embedded Systems," to appear in IEEE Transactions on VLSI Systems. Vol. 57, Issue 12, pp. 1 – 13, Sep, 2011.
  9. Ang-Chih Hsieh and TingTing Hwang, "TSV Redundancy: Architecture and Design Issues in 3D IC," to appear in IEEE Transactions on VLSI Systems. Vol. 20, Issue 4, pp. 711-722, 2012
  10. Shih-Liang Chen, TingTing Hwang, and Wen-Wei Lin, "Randomness Enhancement Using Digitalized Modified-Logistic Map" IEEE Transactions on Circuits and Systems II, Vol. 57, Issue 12, pp. 996 – 1000, Dec, 2010.
  11. Hsien-Te Chen, Chieh-Chun Chang and TingTing Hwang, "Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization," IEEE Transactions on VLSI Systems Vol. 18, Issue 12, pp.1686 – 1695, Dec, 2010.
  12. Shih-Liang Chen, TingTing Hwang, Shu-Ming Chang, Wen-Wei Lin, "A Fast Digital Chaotic Generator for Secure Communication", International Journal of Bifurcation and Chaos, Vol. 20, No. 12, Dec, 2010
  13. M.-C Tsai, T.-C. Wang, and TingTing Hwang, "Through-Silicon Via Planning in 3D Floorplanning, " IEEE Transactions on Very Large Scale Integration Systems, pp.1 – 10, July 2010.
  14. Wen-Wen Hsieh, Shih-Liang Chen, I-Sheng Lin, TingTing Hwang, "A Physical-Location-Aware X-filling Method for IR-Drop Reduction in At-Speed Test," IEEE Transactions on CAD, Volume 14, Issue 2, pp. 289 – 298, Feb. 2010.
  15. Po-Yuan Chen, Chiao-Chen Fang,TingTing Hwang and Hsi-Pin Ma, "Leakage Reduction, Variation Compensation Using Partition-based Tunable Body-Biasing Techniques" ACM Transactions on Design Automation of Electronic Systems, Vol. 14, Issue 4, August 2009.
  16. Po-Yuan Chen, Kuan-Hsien Ho and TingTing Hwang, "Skew Aware Polarity Assignment in Clock Tree," ACM Transactions on Design Automation of Electronic Systems, Volume 14, Issue 2, March 2009.
  17. Shih Liang Chen, S. M. Chang, W. W. Lin and TingTing Hwang, "Digital Secure-communication Using Robust Hyper-chaotic Systems," International Journal of Bifurcation and Chaos, Vol. 18, No. 11, Nov. 2008.
  18. Y.S. Su, P.H. Chang, S.C. Chang, and TingTing Hwang, “Synthesis of a Novel Timing-Error Detection Architecture,” ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 1, Article 14, Jan. 2008.
  19. Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang, "A Bus Encoding Scheme for Crosstalk Elimination in High Performance Processor Design," IEEE Transactions on CAD, Vol 26, Issue 12, pp. 2222-2227, Dec. 2007.
  20. Wu An Kuo, TingTing Hwang and C. H. Wu, "Decomposition of Instruction Decoder for Low Power Design," ACM Transactions on Design Automation of Electronic Systems, Volume 12, No. 4, October 2007.
  21. Ang-Chih Hsieh, Tzu-Ten Lin, Tsuang-Wei Chang and TingTing Hwang, "A Functionality Directed Clustering Technique for Low Power MTCOMS Design – Computation of Simultaneously Discharging Current," ACM Transactions on Design Automation of Electronic Systems, Volume 12, No. 3, Article 30, August 2007.
  22. Yi-Yu Liu and TingTing Hwang,"Crosstalk-aware Domino Logic Synthesis," IEEE Transactions on CAD, Vol.26, I.6, pp.1155-1161, July 2007.
  23. Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, and Allen C.-H. Wu , ”Performance-Driven Crosstalk Elimination at Post-Compiler Level - The Case of Low Crosstalk Op-code,” IEEE Transactions on CAD, Vol. 26, No. 3, pp. 564-573, March 2007.
  24. Yi Yiu Liu, Kuo-Hua Wang and TingTing Hwang, "Crosstalk Minimization in Logic Synthesis for PLA," ACM Transactions on Design Automation of Electronic Systems, Vol. 11(4): pp.890-915, Oct., 2006.
  25. ChiTa Wu, Ang-Chih Hsieh and TingTing Hwang, "Instruction Buffering for Nested Loops in Low Power Design," IEEE Transactions on VLSI Systems, Vol. 14, No. 7, pp. 780-784, July 2006.
  26. Wu-An Kuo, TingTing Hwang, C.H.Wu, "A Power-Driven Multiplication Instruction-Set Design Methods for ASIPs," IEEE Transactions on VLSI Systems, Vol. 14, No. 1, pp. 81-85, January 2006
  27. Wen-Wen Hsieh, Shih-Liang Chen, I-Sheng Lin, TingTing Hwang, "A Physical-Location-Aware X-filling Method for IR-Drop Reduction in At-Speed Test," to appear in IEEE Transactions on CAD .
  28. Hsien-Te Chen, Chieh-Chun Chang and TingTing Hwang, "Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization," to appear in IEEE Transactions on VLSI Systems.
  29. Chingren Lee, Jeng Kuen Lee, TingTing Hwang, and S. Tsai, "Compiler Optimization on VLIW Instruction Scheduling for Low Power," ACM Transactions on Design Automation of Electronic Systems , 8(2): 252-268, 2003.
  30. Ki-Wook Kim, TingTing Hwang, C. L. Liu and Sung-Mo Kang, "Logic Transformation for Low Power Synthesis," ACM Transactions on Design Automation of Electronic Systems , Vol 7, No. 2, pp 265-283, April 2002.
  31. Chau-Shen Chen, TingTing Hwang and C. L. Liu, "Architecture Driven Circuit Partitioning," IEEE Transactions on VLSI Systems , Vol. 9, No. 2, pp. 383-389, April 2001.
  32. How-Rern Lin and TingTing Hwang, "On Determining Sensitization Criterion in an Iterative Gate Sizing Process," IEEE Transactions on CAD, Vol. 18, No. 2, pp. 231-238, Feb. 1999.
  33. Chau-Shen Chen and TingTing Hwang, "Layout Driven Selecting and Chaining of Scan Flip-Flops," Journal of Electronics Testing Theory and Application (JETTA), 13, pp. 19-27, 1998.
  34. Shiuann-Shiuh Lin, Yuh-Ju Lin, and TingTing Hwang, "Net Assignment for Multiple FPGAs in Folded-Clos Interconnection Architecture," IEEE Transactions on CAD, Vol. 16, No. 3, pp. 316-320, March 1997.
  35. Kuo-Hua Wang and TingTing Hwang, "Boolean Matching for Incompletely Specified Functions," IEEE Transactions on CAD, Vol. 16, No. 2, pp. 160-168, Feb. 1997.
  36. Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, and C. L. Liu, "Low Power Realization of Finite State Machines - A Decomposition Approach," ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 3, pp. 315-340, July, 1996.
  37. Kuo-Hua Wang, TingTing Hwang, and Cheng Chen, "Exploiting Communication Complexity for Boolean Matching," IEEE Transactions on CAD, Vol. 15, No. 10, pp. 1249-1256, Oct. 1996.
  38. Shih-Chieh Chang, Malgorzata Marek-Sodowska, and TingTing Hwang, "Technology Mapping for TLU FPGA Based on Decomposition of Binary Decision Diagrams," IEEE Transactions on CAD, Vol. 15, No. 10, pp. 1226-1236, Oct. 1996.
  39. Kuang-Hui Lin, Chau-Shen Chen, and TingTing Hwang, "Layout Driven Chaining of Scan Flip-Flops," IEE Proceedings on Computers and Digital Techniques, Vol. 143, No. 5, Sept. 1996.
  40. How-Rern Lin, Yu-Chin Hsu, and TingTing Hwang, "Cell Height Driven Transistor Sizing in a Cell Based Static CMOS Module Design," IEEE Journal of Solid-State Circuits, Vol. 31, No. 5, pp. 668-676, May 1996.
  41. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C. H. Wu, and Youn-Long Lin, "Combining Technology Mapping and Placement for Delay-minimization in FPGA Designs," IEEE Transactions on CAD, Vol. 14, No. 9, pp. 1076-1084, Sep. 1995.
  42. TingTing Hwang, R. M. Owens, M. J. Irwin, and Kuo-Hua Wang, "Logic Synthesis for Field Programmable Gate Arrays," IEEE Transactions on CAD, Vol. 13, No. 10, pp. 1280-1287, Oct. 1994.
  43. Kuo-Hua Wang, TingTing Hwang, and Cheng Chen, "Technology Mapping for FPGA Using Generalized Functional Decomposition," VLSI Design, Vol. 2, No. 2, pp. 89-103, 1994.
  44. Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, and Youn-Long Lin, "Performance Driven Interconnection Optimization for Microarchitecture Synthesis," IEEE Transactions on CAD, Vol. 13, No. 2, pp. 137-149, Feb. 1994.
  45. Kuo-Hua Wang, TingTing Hwang, and Cheng Chen, "Overlapped Decomposition for Communication Complexity Driven Multi-Level Logic Synthesis," IEICE Transactions on Information and Systems, Vol. E76-D, No. 9, pp. 1075-1084, Sep., 1993.
  46. T. P. Kelliher, R. M. Owens, M. J. Irwin, and TingTing Hwang, "ELM - A Fast Addition Algorithm Discovered by a Program," IEEE Transactions on Computers, Vol. 41, No 9, pp. 1181-1184, Sep., 1992.
  47. TingTing Hwang, R. M. Owens, and M. J. Irwin, "Efficiently Computing Communication Complexity for Multilevel Logic Synthesis," IEEE Transactions on CAD, Vol. 11, No. 5, pp. 545-554, May, 1992.
  48. TingTing Hwang, R. M. Owens, and M. J. Irwin, "Exploiting Communication Complexity for Multilevel Logic Synthesis," IEEE Transactions on CAD, Vol. 9, No. 10, pp. 1017-1027, Oct., 1990.
B. Conference Papers
  1. YenHao Chen, ChienPang Chiu, Russell Barnes and TingTing Hwang, "Architectural Evaluations on TSV Redundancy for Reliability Enhancement," Proceedings of Design, Automation and Test in Europe (DATE), March, 2017.
  2. Chia-Ling Chen, Yen-Hao Chen and TingTing Hwang, "Communication Driven Remapping of Processing Element (PE) in Fault-tolerant NoC-based MPSoCs," The 22nd Asia and South Pacific Design Automation Conference Jan, 2017.
  3. Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C. H. Wu, TingTing Hwang, "A Novel Cache-Utilization Based Dynamic Voltage Frequency Scaling (DVFS) Mechanism for Reliability Enhancements," Proceedings of Design, Automation and Test in Europe (DATE), March, 2016.
  4. Wei-Hen Lo, Kai-zen Liang, TingTing Hwang, "Thermal-aware Dynamic Page Allocation Policy by Future Access Patterns for Hybrid Memory Cube (HMC)," Proceedings of Design, Automation and Test in Europe (DATE), March, 2016.
  5. W. H. Lo, Y. H. Chen, TingTing Hwang, "Dynamic Data Migration to Eliminate Bank-level Interference for Data-parallel Applications in Multicore Systems," Proc. of DAC, June, 2015. (WIP)
  6. W. H. Lo, K. Chi, TingTing Hwang, "Architecture of Ring-based Redundant TSV for Clustered Faults," Proc. of DATE, March, 2015.
  7. P-Yang Hsu, Pei-Lan Lin, TingTing Hwang, "Compaction-free Compressed Cache for High Performance Multi-core System," Proc. of ICCAD, pp. 140-147, Nov., 2014.
  8. Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang, "Fault-tolerant TSV by Using Scan-chain Test TSV," Proc. of ASPDAC, pp.658-663, Jan., 2014.
  9. P-Yang Hsu, TingTing Hwang, "Thread-criticality Aware Dynamic Cache Reconfiguration in Multi-core System," Proc. of ICCAD, pp.413-420, Nov., 2013.
  10. W. H. Lo, A. C. Hsieh, TingTing Hwang, "Utilizing Circuit Structure for Scan Chain Diagnosis," Proc. of European Test Symposium, pp. 1-6, May, 2013.
  11. P-Yang Hsu, Hsien-Te Chen, TingTing Hwang, "Stacking Signal TSV for Thermal Dissipation in Global Routing for 3D IC," Proc. of ASPDAC, pp. 699-704, Jan., 2013.
  12. F. W. Chen and TingTing Hwang, " Clock Tree Synthesis with Methodology of Re-Use in 3-D IC," Proc. of DAC, pp. 1094-1099, June, 2012.
  13. Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Hwang and Yuan Xie, " Thermal-aware Power Network Design for IR Drop Reduction in 3D ICs," Proc. of ASPDAC, pp. 47-52, Feb., 2012.
  14. Ming Chao Tsai and TingTing Hwang, "A Study on the Trade-off among Wirelength, Number of TSV and Placement with Different Size of TSV," Proc. of VLSI-DAT, pp. 66-69, April, 2011.
  15. Ming Chao Tsai and TingTing Hwang, "A Study on the Trade-off among Wirelength, Number of TSV and Placement with Different Size of TSV," Proc. of VLSI-DAT, pp. 66-69, April, 2011.
  16. Hsien-Te Chen, Hung-Lung Lin, Tz-Cheng Wang and TingTing Hwang, "A New Architecture for Power Network in 3D IC," Proc. of Design Automation and Test in Europe Conference, pp. 401– 406, March 2011.
  17. F. W. Chen, Shih-Liang Chen, Yung-Sheng Lin and TingTing Hwang, "A Physical-Location Aware Fault Redistribution for Maximum IR-Drop Reduction" Proc. of ASPDAC, pp. 701–706, Jan. 2011.
  18. Ang-Chih Hsieh, Chun-Cheng Liu, TingTing Hwang, “Enhanced Heterogeneous Code Cache Management Scheme for Dynamic Binary Translation” Proc. of ASPDAC, pp. 231–236, Jan. 2011.
  19. Ang-Chih Hsieh and TingTing Hwang, "Run-Time Reconfiguration of Expandable Cache for Embedded Systems," Proc. of VLSI-DAT, pp. 207-210, April, 2010.
  20. Hsien-Te Chen, W. H. Lo, C. C. Chang and TingTing Hwang, "Placement of Temperature Sensos Under Process Variations," Proc. of VLSI-DAT, pp. 271-274, April, 2010.
  21. Shih-Liang Chen, TingTing Hwang and W. W. Lin, "Randomness Enhancement for a Digitalized Modified-Logistic Map Based Pseudo Random Number Generator," Proc. of VLSI-DAT, pp. 164-167, April, 2010.
  22. Ang-Chih Hsieh and TingTing Hwang, "TSV Redundancy: Architecture and Design Issues in 3D IC," Proc. of Design Automation and Test in Europe Conference, pp. 166-171, March 2010.
  23. Hsien-Te Chen, Chieh-Chun Chang and TingTing Hwang, "New Spare Cell Design for IR Drop Minimization in Engineering Change Order," Proc. of Design Automation Conference, pp. 402-407, July, 2009. (Best paper Candidate)
  24. Po-Yuan Chen, Chiao-Chen Fang,TingTing Hwang and Hsi-Pin Ma, "Leakage Reduction, Variation Compensation Using Partition-based Tunable Body-Biasing Techniques," Proc. of VLSI-DAT, pp. 170-173, April, 2009.
  25. Ang-Chih Hsieh and TingTing Hwang, "Thermal Aware Memory Mapping in 3D Designs," Proc. of Design Automation and Test in Europe Conference, pp. 1361-1366, April, 2009.
  26. Wen-Wen Hsieh and TingTing Hwang, "A Physical-Location-Aware X-filling Method for IR-Drop Reduction in At-speed Scan Test," Proc. of Design Automation and Test in Europe Conference, pp. 1234-1237, April, 2009.
  27. Wen-Wen Hsieh and TingTing Hwang, "Thermal Aware Post-Compilation for VLIW Architecuture," Proc. of ASPDAC , pp. 606-611, Jan. 2009.
  28. Po-Yuan Chen, Che-Yu Liu and TingTing Hwang, "Transition Aware Decoupling-Capacitance Allocation in Power Noise Reduction," Proc. of ICCAD, pp. 426-429, Nov. 2008.
  29. Po-Yuan Chen, Kuan-Hsien Ho and TingTing Hwang, ”Skew Aware Polarity Assignment in Clock Tree,” Proc. of ICCAD, pp. 376-379, Nov., 2007.
  30. Wen-Wen Hsieh,Po-Yuan Chen and TingTing Hwang,”A Bus Architecture for Crosstalk Elimination in High Performance Processor Design,” Proc. of CODES-ISSS 2006, pp 247-252, Oct. 2006.
  31. Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, and Allen C.-H. Wu ,”Performance-Driven Crosstalk Elimination at Compiler Level,” Proc. of ISCAS 2006, pp 3041-3044, Greece, May 2006.
  32. Yi-Yu Liu and TingTing Hwang,"Crosstalk-aware Domino Logic Synthesis," Proc. of DATE, pp 1312-1317, Germany, March 2006.
  33. Yu-Hui Huang, Po-Yuan Chen and TingTing Hwang, "Switching Activity Driven Gate Sizing and Vth Assignment for Low Power Design," Proc. of ASP-DAC, pp. 576-581, Japan, Jan. 2006.
  34. Wu-An Kuo, TingTing Hwang, C.H.Wu, "A Power-Driven Multiplication Instruction-Set Design Methods for ASIPs" Proc. of ISCAS, pp.3311-3314, Japan, May 2005.
  35. Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu, "Low-Power Techniques for Network Security Processors," Proc. of ASP-DAC, pp.355-360, China, 2005.
  36. Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu, "Functionality Directed Clustering for Low Power MTCOMS Design," Proc. of ASP-DAC, pp. 205-208, Japan, Jan. 2005.
  37. Yi-Yu Liu and TingTing Hwang, "Crosstalk Minimization in Logic Synthesis," Proc. of DATE 2004, pp. 790-795, France, Feb. 2004.
  38. Wu An Kuo, TingTing Hwang and C. H. Wu, "Decomposition of Instruction Decoder for Low Power Design," Proc. of DATE 2004, pp. 664-665, France, Feb. 2004.
  39. Chi-Wei Hu and TingTing Hwang, "Output Directed Partitioning for Low Power Design," Proc. of ISCAS 2004, pp. V-137-140, Canada, May 2004.
  40. Yen-Te Ho and TingTing Hwang, "Low Power Design Using Dual Threshold Voltage," Proc. of ASP-DAC 2004, pp. 205-208, Japan, Jan. 2004.
  41. Chi-Wei Hu and TingTing Hwang, "Output Directed Partitioning for Low Power Design," Proc. of ISCAS 2004 , pp. V-137-140, Canada, May 2004.
  42. MingHung Lee, TingTing Hwang, "Decomposition of Extended Finite State Machine for Low Power Design," Proc. of DATE-2003 , Munich, Germany, pp. 1152-1153, 2003.
  43. Y. L. Lo, Allen C. H. Wu and TingTing Hwang, "A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Design," Proc. of DATE-2003 , Munich, Germany, pp.1102-1103, 2003.
  44. C. Y. Chang, Allen C. H. Wu and TingTing Hwang, "G-MAC:An Application-Specific MAC/Co-Processor Synthesizer," Proc. of DATE-2003 , Munich, Germany, pp. 1134-1135, 2003.
  45. Shih-Liang Chen, TingTing Hwang, and C. L. Liu, "A Technology Mapping Algorithm for CPLD Architectures," Proc. of IEEE International Conference on Field Programmable Technology , Hong Kong, pp 204-210, 2002.
  46. ChiTa Wu and TingTing Hwang, "Instruction Buffering for Nested Loop in Low Power Design," Proc. of ISCAS'02 , Arizona, U.S.A., pp. IV81-IV84 2002.
  47. Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang and C. L. Liu, "Binary Decision Diagrams with Minimum Expected Path Length," Proc. of DATE '01 , Munich, Germany, pp. 708-712, 2001.
  48. LiYi Lin, Yi-Yu Liu and TingTing Hwang, "Construction of Minimal Delay Steiner Tree Using Two-pole Delay Model," ASPDAC '01 , Japan, pp. 126-131, 2001.
  49. Chingren Lee, Jeng Kuen Lee, TingTing Hwang, and S. Tsai, "Compiler Optimization on Instruction Scheduling for Low Power," Proc. of ISSS '00 , Madrid, Spain, pp. 55-60, 2000.
  50. Ki-Wook Kim, TingTing Hwang, C. L. Liu and Sung-Mo Kang, "Logic Transformation for Low Power Synthesis," DATE '99, Munich, Germany, pp. 158-162, 1999.
  51. Chau-Shen Chen, TingTing Hwang and C. L. Liu, "Architecture Driven Circuit Partitioning," ICCAD '98, San Jose, CA, pp. 408-411, Nov. 1998.
  52. Jan-Min Hwang, Feng-Yi Chiang, and TingTing Hwang, "A Re-engineering Approach to Low Power FPGA Design Using SPFD," Proc. of DAC '98, San Francisco, pp. 722-725, June 1998.
  53. Chau-Shen Chen, TingTing Hwang and C. L. Liu, "Low Power FPGA Design - A Re-engineering Approach," Proc. of DAC '97, Anaheim, pp. 656-661, June 1997.
  54. TingTing Hwang and Kuo-Hua, "Boolean Matching in Logic Synthesis," Proc. of SASIMI '96, Japan , pp. 57-64, Nov. 1996.
  55. Chau-Shen Chen and TingTing Hwang, "Layout Driven Selecting and Chaining of Scan Flip-Flops," Proc. of DAC '96, Las Vegas, pp. 262-267.
  56. How-Rern Lin and TingTing Hwang, "Power Reduction by Gate Sizing with Path-oriented Slack Calculation," Proc. of ASP-DAC '95, Tokyo, pp. 7-12.
  57. Kuo-Hua Wang and TingTing Hwang, "Boolean Matching for Incompletely Specified Functions," Proc. of DAC '95, San Francisco, CA, pp. 48-53.
  58. How-Rern Lin and TingTing Hwang, "Dynamical Identification of Critical Paths for Iterative Gate Sizing," Proc. of ICCAD '94, pp. 481-484, San Jose, CA, Nov. 1994.
  59. Kuo-Hua Wang, TingTing Hwang, Allen C. H. Wu, and Youn-Long Lin, "State Assignment for Power and Area Minimization," Proc. of ICCD '94, pp. 250-254, Cambridge, MA, Oct., 1994.
  60. How-Rern Lin, Yu-Chin Hsu, and TingTing Hwang, "Cell Height Driven Transistor Sizing in Cell Based Module Design," Proc. of EDAC '94, France, pp. 425-429, March, 1994.
  61. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C. H. Wu, and Youn-Long Lin, "Combining Technology Mapping and Placement for Delay Optimization in FPGA Designs," Proc. of ICCAD '93, pp. 123-127, San Jose, CA, Nov., 1993.
  62. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C. H. Wu, and Youn-Long Lin, "Combining Technology Mapping and Placement for Standard Cell Based Designs," Proc. SASIMI '93, pp. 394-403, Japan, Oct., 1993.
  63. G-S Lee, J-Y Chang, TingTing Hwang, M. J. Irwin, and R. M. Owens, "Synthesis of Multilevel Reed Muller Circuits Using Matrix Transformations," Proc. of IFIP Workshop on Applications of the Reed Muller Expansion in Circuit Design, pp. 61-68, Germany, Sept., 1993.
  64. Kuo-Hua Wang, TingTing Hwang, and Cheng Chen, "Technology Mapping for FPGA Using Generalized Functional Decomposition," Proc. of International Conference of CAD/Graphics '93, pp. 605-610, China, Aug., 1993.
  65. Kuo-Hua Wang, TingTing Hwang, and Cheng Chen, "Restructuring Binary Decision Diagrams Based on Functional Equivalence," Proc. of EDAC '93, pp. 261-265, France, Feb., 1993.
  66. Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, and Youn-Long Lin, "Performance Driven Interconnection Optimization for Microarchitecture Synthesis," Proc. of Euro-DAC '92, pp. 118-123, Germany, Sept., 1992.
  67. Mu-Hoarn Tsai, TingTing Hwang, and Youn-Long Lin, "Technology Mapping for Field Programmable Gate Arrays Using Binary Decision Diagram," Proc. of SASIMI '92, pp. 84-92, Japan, April, 1992.
  68. TingTing Hwang, R. M. Owens, and M. J. Irwin, "Logic Synthesis for Programmable Logic Devices," Proc. of ICCD '90, pp. 364-367, Cambridge, MA, Sep., 1990.
  69. TingTing Hwang, R. M. Owens, and M. J. Irwin, "Multi-Level Logic Synthesis Using Communication Complexity," Proc. of DAC '89, pp. 215-220, Las Vegas, NV, June 1989.
  70. TingTing Hwang, R. M. Owens, and M. J. Irwin, "Communication Complexity Driven Logic Synthesis," Proc. of Inter. Workshop on Logic Synthesis, 14pp., RTP, NC, May 1989.