Ting-Chi Wang

 

A. Journal Papers and Book Chapters

1.      T.-C. Wang and D. F. Wong, Optimal Floorplan Area Optimizatioin,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 8, August 1992, pp. 992-1002.  

2.      T.-C. Wang and D. F. Wong, Graph-Based Techniques to Speed up Floorplan Area Optimization,” INTEGRATION, the VLSI Journal, Vol. 15, No. 2, October 1993, pp. 179-199.  

3.      T.-C. Wang and D. F. Wong, A Note on the Complexity of Stockmeyer’s Floorplan Area Optimization,” Algorithmic Aspects of VLSI Layout (edited by M. Sarrafzadeh and D. T. Lee), World Scientific Publishing Co. Pte. Ltd., 1993, pp. 309-320.

4.      T.-C. Wang, D. F. Wong, Y. Sun and C. K. Wong, Optimal Net Assignment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 2, February 1995, pp. 265-269.

5.      T. W. Her, T.-C. Wang and D. F. Wong, Performance-Driven Channel Pin Assignment Algorithms,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 7, July 1995, pp. 849-857.

6.      Y. Sun, T.-C. Wang, C. K. Wong and C. L. Liu, Routing for Symmetric FPGAs and FPICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 1, January 1997, pp. 20-31.

7.      C. N. Sze and T.-C. Wang, “Optimal Circuit Clustering for Delay Minimization under a More General Delay Model,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 5, May 2003, pp. 646-652.

8.      C. N. Sze, T.-C. Wang and L.-C. Wang, “Multi-Level Circuit Clustering for Delay Minimization,IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 7, July 2004, pp. 1073-1085.

9.      T.-H. Lee and T.-C. Wang, “Congestion-Constrained Layer Assignment for Via Minimization in Global Routing,”   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 9, September  2008, pp. 1643-1656.

10.  T.-C. Wang and M. D. F. Wong, “Slicing Floorplans,Handbook of Algorithms for VLSI Physical Design Automation (edited by C. J. Alpert, D. P. Mehta and S. S. Sapatnekar), CRC Press, 2008, pp. 161-184.

11.  K.-Y. Lee, C.-K. Koh, T.-C. Wang, and K.-Y. Chao, “Fast and Optimal Redundant Via Insertion,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 12, December 2008, pp. 2197-2208.

12.  K.-Y. Lee, S.-T. Lin, and T.-C. Wang, “Enhanced Double Via Insertion Using Wire Bending,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., Vol. 29, No. 2, February 2010, pp. 171-184.

13.  K.-Y. Lee, T.-C. Wang, C.-K. Koh, and K.-Y. Chao, “Optimal Double Via Insertion with On-Track Preference,”  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 2, February 2010, pp. 318-323.

14.  Y.-J. Chang, Y.-T. Lee, J.-R. Gao, P.-C. Wu, and T.-C. Wang, “NTHU-Route 2.0: A Robust Global Router for Modern Designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 29, No. 12, December 2010, pp. 1931-1944.

15.  M.-C Tsai, T.-C. Wang, and T.T. Hwang, “Through-Silicon Via Planning in 3-D Floorplanning,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 8, August 2011, pp. 1448-1457.

16.   W.-K. Mak, Y.-C. Lin, C. Chu, and T.-C. Wang, “Pad Assignment for Die-Stacking System-in-Package Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 11, November 2012, pp. 1711-1722.

17.  C.-R. Li, W.-K. Mak, and T.-C. Wang, “Fast Fixed-Outline 3-D IC Floorplanning with TSV Co-placement”, IEEE Transactions on Very Large Scale Integration(VLSI)  Systems, Vol. 21, No. 3, March 2013, pp.523-532.

18.   C.-H. Liu, C.-X. Lin, I-C. Chen, D. T. Lee, and T.-C. Wang, “Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.33, No.12, December 2013, pp.1928-1941.

19.  W.-H. Liu, T.-K. Chien, and T.-C. Wang, “Region-based and Panel-based Algorithms for Unroutable Placement Recognition,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 4, April 2015, pp. 502-514.

20.  H.-A. Chien, Y.-H. Chen, S.-Y. Han, H.-Y. Lai, and T.-C. Wang, “On Refining Row-Based Detailed Placement for Triple Patterning Lithography,” to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

 

       B. Conference Papers

1.  T.-C. Wang and D. F. Wong, An Optimal Algorithm for Floorplan Area Optimization,” Proceedings of the 27th ACM/IEEE Design Automation Conference (DAC), Orlando, FL, USA, June 1990, pp. 180-186. (Best Paper Candidate)

2.  T.-C. Wang and D. F. Wong, Efficient Shape Curve Construction in Floorplan Design,” Proceeding of European Conference on Design Automation (EDAC), Amsterdam, The Netherlands, February 1991, pp. 356-360.

3.  T.-C. Wang and D. F. Wong, A Graph Theoretic Technique to Speed up Floorplan Area Optimizatioin,” Proceedings of the 29th ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 1992, pp. 62-68.

4.  T.-C. Wang and D. F. Wong, On Stockmeyer’s Floorplan Optimizatioin Technique,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), San Diego, CA, USA, May 1992, pp. 1989-1992.

5.  T.-C. Wang, D. F. Wong, Y. Sun and C. K. Wong, Optimal Channel Density Minimization by Over-the-Cell Routing,” Proceedings of ACM/SIGDA Physical Design Workshop, USA, 1993, pp. 81-92.

6.  Y.-P. Chen, T.-C. Wang and D. F. Wong, Graph Partitioning Problem for Multiple-Chip Design,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), USA, May 1993, pp. 1778-1781.

7.  Y. Sun, T.-C. Wang, C. K. Wong and  C. L. Liu, Routing on Orthogonal Segments,” Proceedings of the 4th VLSI Design/CAD Workshop, Taiwan, 1993, pp. 35-38.

8.  T.-C. Wang,  D. F. Wong, Y. Sun and C. K. Wong, On Over-the-Cell Channel Routing,” Proceedings of EURO-DAC, Hamburg, Germany, September 1993, pp. 110-115.

9.  Y. Sun, T.-C. Wang, C. K. Wong and C. L. Liu, Routing for Symmetric FPGAs and FPICs,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Santa Clara, CA, USA, November 1993, pp. 486-490.

10.   T.-C. Wang and H.-R. Huang, An Effective Codebook Design Algorithm for Entropy-Constrained Vector Quantization Codebook Design,” Proceedings of National Symposium on Telecommunications, Chungli, Taiwan, 1996, pp. 60-67.

11.   T.-C. Wang and H.-R. Huang, A Novel Algorithm for Vector Quantization  Codebook Design,” Proceedings of International Conference on Image Processing and Character Recognition (Joint Conference of International Computer Symposium (ICS)), Kaohsiung, Taiwan, 1996, pp. 145-152.

12.  T.-C. Wang and H.-R. Huang, Designing Better Entropy-Constrained Vector Quantizers via Clustering and Integral Projections,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Hong Kong, May 1997, pp. 1325-1328.

13.  T.-C. Wang, D. F. Wong and C. K. Wong, “A New Channel Pin Asignment Algorithm and Its Application to Over-the-Cell Routing,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Hong Kong, May 1997, pp. 1560-1563.

14.  T.-C. Wang and J.-Y. Chang, “A New Approach to Floorplan Design with Routability Considerations,” Proceedings of the 8th VLSI Design/CAD Symposium, Nangtou, Taiwan, August 1997, pp. 241-244.

15.  C.-F. Cheng and T.-C. Wang, “On Combining Two Fast Codeword Search Algorithms for Vector Quantization,” (in Chinese) Proceedings of the 3rd Symposium on Computer and Communication Technology, Chungli, Taiwan, 1997, pp. 119-127.

16.  T.-C. Wang and H.-R. Huang, “A Fast Two-Phase Algorithm for Vector Quantization Codebook Design,” Proceedings of International Symposium on Multimedia Information Processing, Taipei, Taiwan, 1997, pp. 393-398.

17.   Y.-C. Liu and T.-C. Wang, “An Efficient Algorithm for Vector Quantization Codebook Design Using Clustering and Maximum Descent Techniques,” (in Chinese) Proceedings of National Computer Symposium (NCS), Tainan, Taiwan, 1997, pp. B169-B173.

18.  T.-C. Wang, S.-A. Wen, D. F. Wong and C. K. Wong, “A New Approach to Over-the-Cell Channel Routing,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, May 1998, pp. VI 248–VI 253.

19.  J.-Y. Chang and T.-C. Wang, “Acceleration of Spectral Multi-Way Partitioning,” Proceedings of the 9th VLSI Design/CAD Symposium, Nangtou, Taiwan, August 1998, pp. 327-330.

20.  T.-C. Wang and E.-C. Liu, “An Improved Search-Order Coding Algorithm for Lossless Compression of VQ indexes,” Proccedings of SPIE Electronic Imaging and Multimedia Systems II, Beijing, China, 1998, pp. 171-177.

21.  E.-C. Liu and T.-C. Wang, “Lossless Compression of VQ Indexes Using Search-Order and Correction Codes,” Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), Boston, MA, USA, October 1998, pp. 202-209.

22.  T.-C. Wang and J. Lai, “A Graph-based Approach to Improving Scalar Quantizer Design,” Proceedings of IASTED International Conference on Signal and Image Processing, Las Vegas, NV, USA, October 1998, pp. 173-177.

23.  E.-C. Liu and T.-C. Wang, “An Improvement on Lossless Compression of VQ Indexes,” Proceedings of IEEE Global Communications Conference (GLOBECOM), Sydney, Australia, November 1998, pp. 1699-1703.

24.  J.-Y. Chang, Y.-C. Liu and T.-C. Wang, “Faster and Bester Spectral Algorithms for Multi-Way Partitioning,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Hong Kong, January 1999, pp. 81-84.

25.  S.-C. Tu and T.-C. Wang, “Two-Way Circuit Partitioning with Replication,” Proceedings of the 10th VLSI Design/CAD Symposium, Nangtou, Taiwan, August 1999, pp. 47-50.

26.  J. Lai and T.-C. Wang, “Module Placement with Boundary Constraint Based on BSG-Structure,” Proceedings of the 10th VLSI Design/CAD Symposium, Nangtou, Taiwan, August 1999, pp. 43-46.

27.  M.-F. Shen, S.-Y. Chen, S.-C. Tu and T.-C. Wang, “Two-Way Circuit Partitioning by Iterative Improvement and Logic Perturbation,” Proceedings of IEEE International ASIC/SOC Conference, Wahsington, DC, USA, September 1999, pp. 163-167.

28.  H.-C. Lee and T.-C. Wang, “Feasible Two-Way Circuit Partitioning with Complex Resource Constraints,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2000, pp. 435-440.

29.  E.-C. Liu, T.-H. Lin and T.-C. Wang, “On Accelerating Slicing Floorplan Design with Boundary Constraints,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Geneva, Switzerland, May 2000, III339-III402.

30.  J. Dworak, M. R. Grimaila, B. Cobb, T.-C. Wang, L.-C. Wang, and M. R. Mercer, “On the Superiority of DO-RE-ME / MPG-D Over Stuck-at-Based Defective Part Level Prediction,” Proceedings of the Asian Test Symposium (ATS), Taipei, Taiwan, December 2000, pp. 151-157.

31.  J. Lai, M.-S. Lin, T.-C. Wang and L.-C. Wang,Module Placement with Boundary Constraints Using the Sequence-Pair Representation,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2001, pp. 515-520.

32.  Z.-H. Wang, E.-C. Liu, J. Lai and T.-C. Wang, Power Minimization in LUT-Based FPGA Technology Mapping,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2001,  pp. 635-640.

33.  E.-C. Liu, M.-S. Lin, J. Lai and T.-C. Wang, Slicing Floorplan Design with Boundary-Constrained Modules,Proceedings of ACM International Symposium on Physical Design (ISPD), Sonoma County, CA, USA, April 2001, pp. 124-129.

34.  Y.-H. Jiang, J. Lai and T.-C. Wang, Module Placement with Pre-Placed Modules Using the B*-Tree Representation,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Sydney, Australia, May 2001, Vol. 5, pp. 347-350.

35.  C. N. Sze and T.-C. Wang, “Optimal Circuit Clustering with Variable Interconnect Delay,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, USA, May 2002, pp. IV-707-IV-710.

36.  S. Dhamdhere, N. Zhou and T.-C. Wang, “Module Placement with Pre-Placed Modules Using the Corner Block List Representation,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, USA, May 2002, pp. I-349-I-352.

37.  C. N. Sze and T.-C. Wang, “Multi-Level Circuit Clustering for Delay Minimization,” Proceedings of IEEE/ACM International Workshop on Logic & Synthesis (IWLS), New Orleans, Louisiana, USA, June 2002, pp. 227-232.

38.  C. N. Sze and T.-C. Wang, “Performance-Driven Multi-Level Clustering for Combinational Circuits,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Kitakyushu, Japan, January 2003, pp. 729-734.

39.  W.-Z. Ye, T.-S. Liu and T.-C. Wang, “Enhanced Multi-Level Clustering for Combinational Circuits,” Proceedings of International Workshop on Logic & Synthesis (IWLS), Temecula, California, USA, June 2004, pp. 57-63.

40.  Z.-C. Lu and T.-C. Wang, “Blockage-aware Buffer Insertion with Adaptive Routing Tree Re-construction,” Proceedings of International Workshop on Logic & Synthesis (IWLS), Temecula, California, USA, June 2004, pp. 238-243.

41.  Z.-C. Lu and T.-C. Wang, “Adaptive Routing Tree Reconstruction with Simultaneous Flip-flop and Buffer Insertion,” Proceedings of VLSI Design/CAD Symposium, Pingdong, Taiwan, August 2004.

42.  Y.-L. Lin, P.-H. Yeh and T.-C. Wang, “Discrete Wire Sizing under Current Density Constraints,” Proceedings of VLSI Design/CAD Symposium, Pingdong, Taiwan, August 2004.

43.  Y.-R. Wu, M.-C. Tsai, and T.-C. Wang, “Maze Routing with OPC Consideration,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Shanghai, China, January 2005, pp. 198-203.

44.  Z.-C. Lu and T.-C. Wang, “Concurrent Flip-flop and Buffer Insertion with Adaptive Blockage Avoidance,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Shanghai, China, January 2005, pp. 19-22.

45.  W.-Z. Ye and T.-C. Wang, “Buffered Tree Refinement Considering Timing and Congestion,” Proceedings of IEEE VLSI-TSA International Symposium on VLSI Design, Automation, and Test (VLSI—TSA-DAT), Hsinchu, Taiwan, April 2005, pp. 63-66.

46.  H.-Y. Hsieh, B.-W. Chen and T.-C. Wang, “An Improved Methodology for System-Level Point-to-Point  Communication Architecture Synthesis in SOC Design,” Proceedings of IEEE VLSI-TSA International Symposium on VLSI Design, Automation, and Test (VLSI—TSA-DAT), Hsinchu, Taiwan, April 2005. pp.192-195.

47.  H.-Y. Hsieh and T.-C. Wang, “Simple Yet Effective Algorithms for Block and I/O Buffer Placement in Flip-Chip Designs,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 2005, pp.1879-1882.

48.  K.-Y. Lee, T.-T. Fang and T.-C. Wang, “Yield-Driven Post-Detailed Routing Redundant Via Insertion,” Proceedings of VLSI Design/CAD Symposium, Hualien, Taiwan, August 2005.

49.  T.-T. Fang, S.-Y. Chen and T.-C. Wang, “Concurrent Flip-flop and Buffer Insertuion under Pipeline Constraint,” Proceedings of VLSI Design/CAD Symposium, Hualien, Taiwan, August 2005.

50.  P.-H. Yeh and T.-C. Wang, “Low Power Bus Architecture Synthesis under Performance Constraints,” Proceedings of VLSI Design/CAD Symposium, Hualien, Taiwan, August 2005.

51.  K.-Y. Lee and T.-C. Wang, “Post-Routing Redundant Via Insertion for Yield/Reliability Improvement,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2006, pp. 303-308. (Best Paper Award)

52.  K.-Y. Lee and T.-C. Wang, “Post-Routing Yield/Reliability Improvement by Redundant Via Insertion and End-Line Extension,” Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Nagoya, Japan, April 2006, pp. 465-472.

53.  K.-Y. Lee, T.-C. Wang and K.-Y. Chao, Post-Routing Yield/Reliability Improvement by Redundant Via Insertion with Via Density Consideration,” Proceedings of VLSI Design/CAD Symposium, Hualien, Taiwan, August 2006.

54.  K.-Y. Lee, T.-C. Wang and K.-Y. Chao, “Post-Routing Redundant Via Insertion and Line End Extension with Via Density Consideration,” Proceedings of International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 2006, pp. 633-640.

55.  P.-C. Wu, J.-R. Gao and T.-C. Wang, “A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2007, pp. 262-267.

56.  T.-T. Fang and T.-C. Wang, “Fast Buffered Delay Estimation Considering Process Variations,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2007, pp. 702-707.

57.  C.-W. Lin, M.-C. Tsai, K.-Y. Lee, T.-C. Chen, T.-C. Wang, and Y.-W. Chang, “Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2007, pp. 238-243.

58.  K.-Y. Lee, T.-C. Wang and K.-Y. Chao, “Optimal Redundant Via Insertion Using Mixed Integer Linear Programming,” Proceedings of VLSI Design/CAD Symposium, Hualien, Taiwan, August 2007, pp. 310-313.

59.  T-Y. Hsu, T.-C. Wang and K.-Y. Lee, Power-Aware Memory Mapping for FPGAs,” Proceedings of VLSI Design/CAD Symposium, Hualien, Taiwan, August 2007, pp. 593-596.

60.  K.-Y. Lee, T.-C. Wang and K.-Y. Chao, “A Mixed Integer Linear Programming Based Approach for Post-Routing Redundant Via Insertion,” Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Sapporo, Japan, October 2007, pp. 184-191.

61.  S.-Y. Chen and T.-C. Wang, “Blockage-Aware Routing Tree Construction with Concurrent Buffer and Flip-Flop Insertion,” Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Sapporo, Japan, October 2007, pp. 147-154.

62.  J-R. Gao, P.-C. Wu and T.-C. Wang, “A New Global Router for Modern Designs,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, January 2008, pp. 232-237.  

63.  M.-C. Tsai, Y.-C. Lin and T.-C. Wang, “An MILP-Based Wire Spreading Algorithm for PSM-Aware Layout Modification,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, January 2008, pp. 364-369.

64.  K.-Y. Lee, C.-K. Koh, T.-C. Wang, and K.-Y. Chao, “Optimal Post-Routing Redundant Via Insertion,” Proceedings of International Symposium on Physical Design (ISPD), Portland, Oregon, USA, April 2008, pp. 111-117.  (Best Paper Candidate)

65.  T.-Y. Hsu and T.-C. Wang, “A Generalized Network Flow Based Algorithm for Power-Aware FPGA Memory Mapping,” Proceedings of Design Automation Conference (DAC), Anaheim, California, USA, June 2008, pp. 30-33.

66.  Y.-J. Chang, Y.-T. Lee, and T.-C. Wang, “NTHU-Route 2.0: A Fast and Stable Global Router,” Proceedings of International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, November 2008, pp. 338-343.

67.  Y.-C. Lin, K.-Y. Lee, and T.-C. Wang, “A Two-Layer Global Router for Ball Grid Array Packages,”  Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Okinawa, Japan, March 2009, pp. 301-306.  

68.  Y.-R. Wu, S.-Y. Chen, K.-Y. Lee, and T.-C. Wang, “On Using Spare Cells for Functional Changes with Wirelength Consideration,” Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Okinawa, Japan, March 2009, pp. 64-69.

69.  K.-Y. Lee, S.-T. Lee, and T.-C. Wang, “Redundant Via Insertion with Wire Bending,” Proceedings of International Symposium on Physical Design (ISPD), San Diego, California, USA, March  2009, pp. 123-130.

70.  T.-H. Lee and T.-C. Wang, “Robust Layer Assignment for Via Optimization in Multi-layer Global Routing,” Proceedings of International Symposium on Physical Design (ISPD), San Diego, California, USA, March  2009, pp. 159-166.

71.  M.-C Lan, J.-M. Shyu, T.-C. Wang, and C. Su, “Education Program for VLSI Design in Taiwan”, Proceedings of International Conference on Engineering Education & Research (ICEER), Seoul, Korea, August 2009.

72.  Y.-C. Lin, W.-K. Mak, C. Chu, and T.-C. Wang, “Pad Assignment for Die-Stacking System-in-Package Design”, Proceedings of International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, November 2009, pp. 249-255.

73.  Y.-T. Lee, Y.-J. Chang, and T.-C. Wang, “A Temperature-Aware Global Router,” Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 2010, pp. 279-282.

74.  D.-Y. Liu, W.-K. Mak, and T.-C. Wang, “Temperature-Constrained Fixed-Outline Floorplanning for Die-Stacking System-in-Package Design,” Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), Providence, Rhode Island, USA, May 2010, pp. 423-428.

75.  M.-C. Tsai, T.-C. Wang, and T.T. Hwang, “Through-Silicon Via Planning in 3D Fixed-Outline Floorplanning,” Proceedings of International Conference on Green Circuits and Systems (ICGCS), Shanghai, China, June 2010, pp. 584-588.

76.  T.-H. Lee and T.-C. Wang, “Simultaneous Antenna Avoidance and Via Optimization in Layer Assignment of Multi-layer Global Routing,” Proceedings of International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, November 2010, pp. 312-318.

77.  Y.-J. Chang, T.-H. Lee and, T.-C. Wang, “GLADE: A Modern Global Router Considering Layer Directives,” Proceedings of International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, November 2010, pp. 319-323.

78.  S.-T. Lin, K.-Y. Lee, T.-C. Wang, C.-K. Koh, and K.-Y. Chao, “Simultaneous Redundant Via Insertion and Line End Extension,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January 2011, pp. 633-638.

79.  T.-H. Lee, Y.-J. Chang, and T.-C. Wang, “An Enhanced Global Router with Consideration of General Layer Directives,” Proceedings of International Symposium on Physical Design (ISPD), Santa Barbara, California, USA, March  2011, pp. 53-60.

80.    C.-Y. Hong, W.-K. Mak, and T.-C. Wang, “Temperature-Constrained Fixed-Outline Floorplanning for 3D ICs”, Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Beppu, Oita, Japan, March 2012, pp. 457-459.

81.    B.-H. Zeng, R.-S. Tsay, and T.-C. Wang, “An Efficient Hybrid Synchronization Technique for Scalable Multi-Core Instruction Set Simulations,” Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, January, pp. 588-593.

82.    H.-J. Chou, H.-A. Chien, and T.-C. Wang, “A Global Router Considering Scenic Controls, Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Sapporo, Hokkaido, Japan, October 2013, pp. 153-158.

83.    H.-A. Chien, and T.-C. Wang, “Redundant-Via-Aware ECO Routing,Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), Singapore, January 2014, pp. 418-423. (Best Paper Candidate)

84.     W.-H. Liu, T.-K. Chien and T.-C. Wang, “Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost,” Proceedings of Design, Automation & Test in Europe (DATE), Dresden, Germany, March 2014.

85.    H.-A. Chien, Z.-Y. Peng, Y.-R. Wu, T.-H. Wang, H.-C. Lin, C.-F. Wu and T.-C.Wang, Mask-Cost-Aware ECO Routing,Proceedings of Design, Automation & Test in Europe (DATE), Dresden, Germany, March 2014.

86.    W.-H. Liu, T.-K. Chien and T.-C. Wang, “A Study on Unroutable Placement Recognition, Proceedings of International Symposium on Physical Design (ISPD), Petaluma, California, USA, March 2014, pp. 19-26.

87.    R. Ewetz, W.-H. Liu, K.-Y. Chao, T.-C. Wang, and C.-K. Koh,  “A Study on the use of Parallel Wiring Techniques for Sub-20nm Designs,Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), Huston, Texas, USA, May 2014, pp. 129-134.

88.    W.-H. Liu, M.-S. Chang, and T.-C. Wang, “Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs,Proceedings of Design Automation Conference (DAC), San Francisco, California, USA, June 2014.

89.    S. Popovych, H.-H. Lai, C.-M. Wang, Y.-L. Li, W.-H. Liu, and T.-C. Wang, “Density-aware Detailed Placement with Instant Legalization,Proceedings of Design Automation Conference (DAC), San Francisco, California, USA, June 2014.

90.    W.-H. Liu, Z.-Y. Peng, and T.-C. Wang, “A Resource-level Parallel Approach for Global-routing-based Routing Congestion Estimation and a Method to Quantify Estimation Accuracy,” International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, November 2014, pp.389-396.

91.    H.-Y. Lai and T.-C. Wang, “A TPL-Friendly Legalizer for Standard Cell Based Design,” Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Yilan, Taiwan, March 2015, pp. 100-105.

92.    H.-A. Chien, S.-Y. Han, Y.-H. Chen, and T.-C. Wang, “Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography,” Proceedings of International Symposium on Physical Design (ISPD), Monterey, California, USA, March-April  2015, pp. 67-74. (Best Paper Candidate)

 

                C. Patents

1. C.-L. Ding, T.-C. Wang and M. J. Irwin, Cell Placement Method for Microelectronic Integrated Circuit Combining Clustering, Cluster Placement and De-Clustering, USA Patent 5,682,321, October 28, 1997.

2. K.-Y. Lee and T.-C. Wang, Method for Post-Routing Redundant Via Insertion in Integrated Circuit Layout, USA Patent  7,302,662, November 27, 2007.

3. 王廷基, 李光曜, 用於積體電路佈局之繞線後階段冗餘介層洞插入之方法」, 中華民國專利I 323416, April 11, 2010.