(A)   Journal Publication

  1. S.C. Chang, M. Marek-Sadowska and T.T. Hwang, "Technology mapping for TLU Type FPGA based on decomposition of Binary Decision Diagram," IEEE Transaction on Computer Aided Design, pp. 1126-1236, Oct., 1996.
  2. S.C. Chang, M. Marek-Sadowska, and K.T. Cheng, "Perturb and Simplify: Multi-level Boolean Network Optimizer," IEEE Transaction on Computer Aided Design, Vol. 15, pp. 1494-1504, Nov., 1996.
  3. S.C. Chang, K.T. Cheng, N.S. Woo, and M. Marek-Sadowska, "Post Layout Logic Restructuring Using Alternative Wires," IEEE Transaction on Computer Aided Design, Vol. 16, pp. 587-596, 1997.
  4. S. C. Chang and I. H. Cheng, “Efficient Boolean Division and Substitution Using Redundancy Addition and Removal,”IEEE Transaction on Computer Aided Design, Vol. 18, pp. 1096-1106, 1999.
  5. S.C. Chang, L.V.Ginneken, and M. Marek-Sadowska, "Circuit Optimizations by Rewiring," IEEE Transaction on Computer, Vol. 48, pp. 962-970, 1999.
  6. S.C. Chang, W.B. Jone and S.S. Chang, “TAIR: Testability Analysis by Implication Reasoning,”IEEE Transaction on Computer Aided Design, Vol. 19, pp. 152-160, 2000.
  7. S.C. Chang, K.J. Lee, Z.Z. Wu, and W.B.Jone, "Reducing Test Application Time by Scan Flip-Flop Sharing," IEE proceeding-Computes and Digital Techniques, Vol. 147, pp. 42-52, Jan., 2000
  8. J. C. Rau, W. B. Jone, S. C. Chang, and Y. L. Wu, "A Tree-Structured LFSR Synthesis Scheme for Pseudo-Exhaustive Testing of VLSI Circuits," IEE Proceedings - Computers and Digital Techniques, Vol.147 - (5), pp. 343-348, Sep. 2000.
  9. C.H. Cheng, W.B. Jone, S. C. Chang, and J. S. Wang,“Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits,” IEE Electronics Letters, Vol. 36, No. 20, pp. 1684-1685, Sep. 2000.
  10. S.C. Chang, and J.C. Rau, "A Timing Driven Pseudo Exhaustive Testing for VLSI circuits," IEEE Transaction on Computer Aided Design, Vol. 20, pp. 147-157, Jan. 2001.
  11. S. C. Chang, K. Y. Chen, W.B. Jone and S. R. Das "Random pattern testability enhancement by circuit rewiring" VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, vol. 12, no. 4, pp. 537-549, Dec. 2001.
  12. W. B. Jone, D. C. Huang, S. C. Chang and S. R. Das, “Defect Level Estimation for Pseudorandom TestingUsing Stochastic Analysis,” VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, vol.12, no. 4, pp. 457-474, Dec. 2001.
  13. S. C. Chang, C,H. Cheng, W.B. Jone, S.D. Li and J.S. Wang, "Charge Sharing Alleviation and Detection for CMOS Domino Circuits," IEEE Transaction on Computer Aided Design, Vol 20, pp. 266-280, 2001. Paper is included in Signal Integrity Effects in Custom IC and ASIC Designs, edited by R. Singh, Publisher: Wiley Inter-Science 2002
  14. S.C. Chang, Z. Z. Wu, "Theorems and Extensions of Single Wire Replacement," IEEE Transaction on Computer Aided Design, Vol. 20, pp. 1159-1163, 2001.
  15. Z.Z. Wu, S.C. Chang, “Synthesis for Multiple Input Wire Replacement of a Gate: Theorems and Applications,” IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, No. 12, pp. 3116-3124, 2001.
  16. C.H. Cheng, T.K. Tien, Y.C. Shen, and S.C. Chang, “Functional Slack Time Computation of Logic Gate” Journal of the Chinese Institute of Electrical Engineering VOL. 8, NO. 4, pp. 325-334, November 2001.
  17. S.C. Chang, D. I. Cheng, C.W. Yeh, “Removing multiple redundancies in combinational circuits” IEE Proceedings Computers and Digital Techniques, Volume: 149, pp.-8, Jan. 2002.
  18. Y. H. Su, C. H. Cheng, and S. C. Chang, "Novel Techniques for Improving Testability Analysis," Transactions on Fundamentals of Electronics, Communications and Computer Sciences (IEICE) Vol.E85-A, No. 12, pp. 2901-2912, 2002.
  19. T.K. Tien, S.C. Chang and T.K. Tsai, "Crosstalk Alleviation for Dynamic PLAs," IEEE Transaction on Computer-Aided Design, Vol. 21, pp. 1416-1424, December 2002.
  20. J. H. Jiang, W. B. Jone, S. C. Chang, and S. Ghosh, “Embedded Core Test Generation Using Broadcast Test Architecture and Netlist Scrambling,” IEEE Transaction on Reliability, Vol. 52, No. 4, pp. 435-443, 2003.
  21. C.T. Hsieh, J.C. Lin, and S.C. Chang, "A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits IEEE Transaction on CAD, Vol. 25, No. 11, pp. 2341-2352, 2006
  22. Z. Z. Wu, H. J. Yu, and S. C. Chang "Wire Reconnection Based on Implication Flow Graph," accepted in ACM Transaction on Design Automation of Electronic Systems.
  23. T.K. Tien, C.S. Tsai, S.C. Chang, and C.W. Yeh, “Power Minimization for Dynamic PLAs,” IEEE Trans. VLSI Systems, vol. 14, no. 6, pp. 616-624, June 2006.

 

 

(B)Conference Publication

  1. S.C. Chang and M. Marek-Sadowska, "Technology Mapping via Transformation of Function Graphs", Proc. IEEE/ACM  International Conference on Computer Design, ICCD, pp.159-162, 1992.
  2. S.C. Chang and M. Marek-Sadowska, "Technology Mapping and Circuit Depth Optimization for Field Programmable Gate Array", Proc. CICC, pp. 3.5.1-3.5.4, 1993.
  3. S.C. Chang and M. Marek-Sadowska, "BDD Representation of Incompletely Specified Functions", International Workshop on Logic Synthesis, 1993.
  4. D.I. Cheng, S.C. Chang and M. Marek-Sadowska, "Partitioning Combinational Circuits in Graph and Logic Domains", Proc. SASIMI, pp 404-412, 1993.
  5. S.C. Chang, David Ihsin Cheng, and M. Marek-Sadowska, "Minimizing ROBDD size of Incompletely Specified functions", Proc. IEEE/ACM,  Europe Design Automation Conference, EDAC, pp 620-624,1994.
  6. S.C. Chang, K-T Cheng, Nam-Sung Woo and M. Marek-Sadowska,  "Layout Driven Logic Synthesis for FPGA," Proc. IEEE/ACM Pro. Design Automation Conference, DAC, pp. 308-313.
  7. S.C. Chang and M. Marek-Sadowska,  "Perturb and Simplify: Multi-level Boolean network Optimizer," Proc. IEEE/ACM  International Conference on Computer Aided Design, ICCAD,  pp. 2-5, 1994.
  8. C-C Lin, K.C. Chen, S.C. Chang, and M. Marek-Sadowska, "Logic Synthesis for engineering Change", Proc. IEEE/ACM Pro. Design Automation Conference, DAC, pp. 647-652,1995.
  9. S.C. Chang, K-T Cheng and M. Marek-Sadowska, "An efficient algorithm for local don't cares calculation," Proc. IEEE/ACM Pro. Design Automation Conference, DAC,  pp. 663-667, 1995.
  10. S.C. Chang, M. Marek-Sadowska, "Perturb and Simplify: Optimizing Circuits with External Don't Cares", Proc. IEEE/ACM, Europe Design Automation Conference, EDAC, pp. 8a-1, 1996.
  11. S.C. Chang, L.Van Ginneken, and M. Marek-Sadowska, "Fast Boolean Optimization by Rewiring," Proc. IEEE/ACM, International Conference on Computer Aided Design, ICCAD, pp. 262-269, 1996.
  12. C.W. Yeh, M.C. Chang, S.C. Chang, W.B. Jone, and J.S. Wang, "Reducing Power Consumption by Iterative Gate Sizing and Voltage Scaling," Proc. The 8th VLSI Design/CAD Symposium, pp.281-283, 1997.
  13. S.C. Chang, I. Cheng, C.W. Yeh, "On Removing Multiple Redundancies in Combinational Circuits," Proc. IEEE/ACM Design, Automation and Test in Europe, DATE, pp. 738-742, Feb., 1998.
  14. S. C. Chang, and I. Cheng, "Efficient Boolean Division and Substitution ," Proc. IEEE/ACM Pro. Design Automation Conference DAC, pp. 342-347, 1998.
  15. W.B. Jone, J.C. Rau, S.C. Chang, and Y.L. Wu, "A Tree-Structured LFSR Synthesis Scheme for Pseudo-Exhaustive Testing of VLSI Circuits," Proc. IEEE International Test Conference, ITC, pp. 22-330, 1998.
  16. S.C. Chang, S.S. Chang, W.B. Jone, and C.C Tsai, “A Novel Combinational Testability Analysis by Considering Signal Correlation," Proc. IEEE International Test Conference, ITC, pp. 658-667, 1998.
  17. S.C. Chang, S.S. Chang, W. B. Jone, and C.C. Tsai, “An Efficient Technique for Enhancing Combinational Testability Measurement,”Proc. The 9th VLSI Design/CAD Symposium, pp. 145-148, 1998.
  18. S.C. Chang, K.Y. Chen, W.B. Jone, and S.R. Das, “Random Pattern Testability Enhancement by Circuit Rewiring," Proc. IEEE  International conference on VLSI design, pp. T9.4, 1999.
  19. C.W. Yeh, M.C. Chang, S.C. Chang, and W.B. Jone, “Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications,” Proc. Design Automation Conference DAC, pp. 68-71, 1999.
  20. C. H. Cheng, S. C. Chang, J. S. Wang and W. B. Jone, “Charge Sharing Fault Detection for CMOS Domino Logic Circuits,” Proc. International Symposium on Defect & Fault Tolerance in VLSI System, pp. 77-85, 1999.
  21. C.W. Yeh, M.C. Chang, S.C. Chang, and W.B. Jone, “Power Reduction Through Iterative Gate Sizing and Voltage Scaling” IEEE International Symposium on circuits and Systems, ISCAS Vol I, pp. 246-249, 1999.
  22. S.C. Chang, K. J. Lee, Z. Z. Wu, and W. B. Jone, "Test Application Time Reduction by Input Signal Sharing,”Proc. The 10th VLSI/CAD symposium, pp. 115-118, 1999.
  23. C.H. Cheng, S.C. Chang, J.S. Wang, and W.B. Jone, "Charge Sharing Fault Detection for CMOS Domino Logic Circuits," Proc. The 10th VLSI/CAD symposium, pp. 175-178, 1999.
  24. S.C. Chang, J.C. Chuang, and Z.Z. Wu, “Multiple Input Wire Replacement for Wiring Consideration,” Proc. IEEE/ACM,  International Conference on Computer Aided Design, ICCAD, pp. 115-118, 1999.
  25. S.C. Chang, and J.C.Rau, "A Timing-Driven Pseudo-Exhaustive Testing of VLSI Circuits," Proc. of IEEE International Symposium on Circuits And Systems, vol. II, pp. 665-668, 2000.
  26.  J.C.Rau, Y.M.Chen, and S.C. Chang, "A Compact Factored Form for a Boolean   Function," Proc. of IEEE International symposium on Circuits And Systems, vol. II, pp. 317-320, 2000.
  27. C. H. Cheng, J. S. Wang, S. C. Chang, and W. B. Jone, "Charge Sharing Fault Analysis and Testing for CMOS Domino Logic," 1st IEEE Latin-American Test Workshop, pp. 59-64, 2000.
  28. C. H. Cheng, J. S. Wang, S. C. Chang, and W. B. Jone, "Scan-Resistant Charge-Sharing Fault in Domino Circuit," IEEE Computer Society Annual Workshop on VLSI.
  29. S. C. Chang, Z. Z. Wu, and H. J. Yu, "Wire Reconnection Based on Implication Flow Graph," Proc. IEEE/ACM,  International Conference on Computer Aided Design, ICCAD, pp. 533-537, 2000.
  30. C. H. Chen, S. C. Chang, S. T. Le, W. B. Jone, and J.S. Wang, "Synthesis of CMOS Domino Circuits for Charge Sharing alleviation," Proc. IEEE/ACM, International Conference on Computer Aided Design, ICCAD, pp. 387-340, 2000.
  31. C. H. Cheng, J.S. Wang, S.C. Chang, and W.B. Jone, "Charge Sharing Fault Analysis and Testing for CMOS Domino Logic," Proc. IEEE the Ninth Asian Test Symposium, ATS, PP. 435-440, 2000.
  32. Y.H. Su, C. H. Cheng, S.C. Chang, and C.W. Yeh, "Novel Techniques for Improving Testability Analysis, " Proc. IEEE the Ninth Asian Test Symposium, ATS, PP. 392-397, 2000.
  33. J. H. Jiang, W. B. Jone, and S. C. Chang,“Embedded Core Testing Using Broadcast Test Architecture,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 95-103, DFT2001.
  34. J.C. Rau, J. H. Wang, and S. C. Chang, "Logic Optimization of Circuits with Pre-defined Internal Don't Cares", Proc. of IEEE International Symposium on Circuits And Systems, vol. I, pp. 237-240, 2001.
  35. T. K. Tien, S.C. Chang and T.K. Tsai, "Crosstalk Alleviation for Dynamic PLAs," Proc. IEEE/ACM Design, Automation and Test in Europe DATE, pp. 683-687, 2002.
  36. T. K. Tien, C.C. Hsu, Y.Y. Liu and S.C. Chang, "Timing Optimization for Dynamic PLAs by Reordering Lines," 13th VLSI/CAD symposium 2002.
  37. S.C. Chang, J.D. Shieh, and K.C. Wu, “Re-synthesis for Delay Variation Tolerance,” Proc. IEEE/ACM Pro. Design Automation Conference, DAC, pp. 814-819, 2004. (power point)
  38. S. Ghosh, K. W. Lai, W. B. Jone, S. C. Chang, “Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits,” ATS 2004.
  39. C.T. Hsieh, J.C. Lin, and S.C. Chang, "A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits," Proc. IEEE/ACM International Conference on Computer Aided Design, ICCAD,  pp.537-540, 2004. (power point)
  40. C.H. Lin, Y.C Huang, S.C Chang and W.B. Jone, “Design and Design Automation of Rectification Logic for Engineering Change,” Asia South Pacific Design Automation, ASPDAC, pp. 1006-1009, 2005.
  41. T.K. Tien, C.S. Tsai, S.C. Chang, and C.W. Yeh, “Power Minimization for Dynamic PLAs,” Asia South Pacific Design Automation, ASPDAC, pp. 1010-1013,  2005.
  42. Y.F. Lee, S.Y. Huang, S.Y. Hsu, I.L. Chen, and C.T. Shieh, J.C. Lin, and S.C. Chang, “Power Estimation Strategies For A Low-Power Security Processor,” Asia South Pacific Design Automation, ASPDAC, pp. 367-371 2005.
  43. Y. L. Huang, C.Y. Wang, Richard Yeh and S. C. Chang, “Language-Based High Level Transaction Extraction on On-chip Buses,” International Symposium on Quality Electronic Design, ISQED, 2006.
  44. C.T. Hsieh, K.C. Wu, and S.C. Chang, “Delay Variation Tolerance for Domino Circuit,” Asia South Pacific Design Automation, ASPDAC, pp. 354-359, 2006. (power point)
  45. C. H. Lin, C. T. Huang, C. P. Jiang, and S. C. Chang, “Optimization of Regular Expression Pattern Matching Circuits on FPGA" Proc. IEEE/ACM Design, Automation and Test in Europe,  DATE, pp. 12-17, 2006. (power point)
  46. D.S. Chou, S.H, Chen, S.C. Chang, C.W. Yeh, “Timing Driven Power Gating,” Prof. IEEE/ACM Design Automation Conference, pp.121- 124, 2006 (power point)
  47. Y.M. Kuo, Y.L. Chang, S.C. Chang, “Efficient Boolean Characteristic Function For timed ATPG,” accepted to Proc. IEEE/ACM International Conference on Computer Aided Design, ICCAD, 2006.