Hsinchu, Taiwan, R.O.C., December 2-4, 1998

Sponsored by the IEEE Computer Society DATC and the ACM SIGDA

Important Dates
Advance Registration Deadline:November 10, 1998
Hotel Reservation Deadline:November 10, 1998
On-Site Registration:December 1-4, 1998

About ISSS
ISSS is a major international forum presenting emerging techniques for the system-level design and synthesis of computing systems. Having begun as the International Workshop on High-Level Synthesis in the mid-80's, it attracts leading design automation professionals from around the world. The growing acceptance of commercial synthesis tools, and the unified view of both hardware and software that such tools enable, have led to the symposium expanding to now cover system-level synthesis, hardware/software codesign, programmable (multi-)processor-based design, architectural and high-level synthesis, system-design experience and methodologies, embedded and real-time system software, synthesis for low power and testability and verifiability ISSS'98 is the 11th in this very successful series of symposia. It features 5 invited talks by leading industrial and academic experts on very timely and interesting topics related but not overlapping with the other ISSS activities. In addition, 1 panel session is organized on topics of active interest for the future of our community. ISSS'98 also features 24 high-quality regular and poster papers selected from over 60 submissions. Paper presentations will consist of 20 minute talks followed by poster sessions, allowing ample time for discussion and interaction.

Technical Program

Tuesday, December 1, 1998
18:00 - 20:00On-site Registration
19:00 - 21:00Reception
Wednesday, December 2, 1998
08:30 - 09:00Open statement
09:00 - 10:00Invite talk
Is IP Business Hype or Reality?
Prof. D. D. Gajski, U. of California, Irvine, USA
10:00 - 10:30Coffee break
10:30 - 11:30Session 1: Code Generation and Optimization Issues
1.1 A Uniform Optimization Technique for Offset Assignment Problems
Rainer Leupers, Fabian David; Dept. of Computer Science,Univ. of Dortmund
1.2 Code Generation for Compiled Bit-True Simulation of DSP Applications
L. De Coster, M. Ade, R. Lauwereins, J.A. Peperstraete; Katholieke Univ. Leuven, Dept. ESAT, Belgium
1.3 Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture
W.-K. Cheng, Y.-L. Lin; Dept. of CS, NTHU, Taiwan, R.O.C
11:30 - 12:00Poster discussion
12:00 - 13:30Lunch
13:30 - 14:30Invite talk
Issues in Embedded DRAM Development and Applications
Dr. K.-S. Doris; Siemens Research and Devel, Germany
14:30 - 15:30Session 2: IP Reuse and Language
2.1 A Processor Description Language Supporting Retargetable Multi-Pipeline DSP Program Development Tools
C. Siska; Rockwell Semiconductor Systems, Inc.
2.2 Intellectual Property Re-use in Embedded System Co-design: an Indutrial Case Study
E. Filippi, L. Lavagno, L. Licciardi, A. Montanaro, M. Paolini, R. Passerone, A. Sangiovanni-Vincentelli, M. Sgroi; CSELT, Italy. Dipartimento di Elettronica, Politecnico di Torino, Italy. Univ. of CA. at Berkeley, USA.
2.3 Incorporating Cores into System-Level Specification
F. Vahid and T. Givargis; Dept. of Computer Science, Univ. of California, USA
15:30 - 16:00Poster discussion and coffee break
16:00 - 16:30Poster presentation
P1 HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation
R. Leupers; Dept. of Computer Science, Univ. of Dortmund
P2 False Path Analysis based on a Hierarchical Control Representation
A. A. Kountouris and C. Wolinski; IRISA - Institut de Recherche en Informatique et Systemes Aleatoires
P3 Resource constrained Modulo Scheduling with Global Resource Sharing
C. Jaeschke, R. Laur; Univ. of Bremen, Dept. 1, Institute of Electromagnetic Theory and Micro., Bremen/Germany.
P4 Statistical Performance-Driven Module Binding in High-Level Synthesis
H. Tomiyama, A. Inoue, and H. Yasuura; Dept. of Computer Science and Communication Eng., Graduate School of Information Science and Electrical Eng., Kyushu Univ., Japan.
P5 Concurrent Error Detection at Architectural Level
C. Bolchini, W. Fornaciari, F. Salice, D. Sciuto; Cristiana Bolchini: Politecnico di Milano-Dipartimento di Elettronica e Informazione, Italy.
P6 Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System Y.-T. Hwang, Y.-H. Wang; Dept. of Electronic Eng. NYU of Science & Technology Taiwan, R.O.C.
16:30 - 17:30Poster discussion
18:30 - 20:00Dinner
20:00 - 22:00Panel and Beer
IP-Based design: VIP (Very Important Process) or RIP(Rest in Peace)
Thursday, December 3, 1998
09:00 - 10:00Invite talk
Compiler Technology for Application-Specific Processors/Systems on Chips
Prof. Monica Lam, Stanford Univ., USA
10:00 - 10:30Coffee break
10:30 - 11:30Session 3: Application-Specific Synthesis Techniques
3.1 Application-Specific Heterogenous Multiprocessor Synthesis Using Differential-Evolution
A. Rae, S. Parameswaran; Dept. of Computer Science and Electrical Eng. Univ. of Qu`ensland, Australia.
3.2 Proposal for unified system design meta flow in task-level and instruction-level design technology research for multi-media applications
F. Catthoor, D. Verkest, E. Brockmeyer; IMEC, VSDM Division, Katholieke Univ. Leuven
3.3 Data-path Synthesis of VLIW Video Signal Processors
Z. Wu, W. Wolf; Dept. of Electrical Eng., Princeton Univ., U.S.A.
11:30 - 12:00Poster discussion
12:00 - 13:30Lunch
13:30 - 14:30Group discussion
14:30 - 15:30Session 4: Synchronization and Interface Issues
4.1 Synchronization Detection for Multi-Process Hierarchical Synthesis
O Bringmann, W. Rosenstiel, D. Reichardt; FZI and Univ. of Tubingen, Germany
4.2 Integrating Communication Protocol Selection with Partitioning in Hardware/Software Codesign
P. V. Knudsen and J. Madsen; Dept. of Information Technology, Technical Univ. of Denmark, Denmark
4.3 Interface Exploration for Reduced Power in Core-Based Systems
T. Givargis, F. Vahid; Dept. of Computer Science, University of California, U.S.A.
15:30 - 16:00Poster discussion and coffee break
16:00 - 17:00Session 5: Instruction Encoding and Software Synthesis Techniques
5.1 Instruction Encoding Techniques for Area Minimization ofInstruction ROM
T. Okuma, H. Tomiyama, A. Inoue, E. Fajar, H. Yasuura Dept. of Computer Science and Communication Eng., Kyushu University, Japan
5.2 Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Alloation
I.-J. Huang, P.-H. Xie; Institute of Computer and Information Eng., NSYSU Kaohsiung, Taiwan, R.O.C.
5.3 Memory Efficient Software Synthesis from Dataflow Graph
W. Sung, Junedong Kim, Soonhoi Ha; Dept. of Computer Eng., Seoul National University, Korea
17:00 - 17:30Poster discussion
17:30 - 18:30General discussion session
19:00 - 21:00Banquet
Friday, December 4, 1998
09:00 - 10:00Invite talk (TBA)
Mr. Miin Wu, Macronix International Co., Ltd, Taiwan.
10:00 - 10:30Coffee break
10:30 - 11:30Session 6: Partitioning and Scheduling Techniques
6.1 A Tool Partitioning and Pipelined Scheduling of Hardware-Software Systems
Karam S. Chatha and Ranga Vemuri; Laboratory for Digital Design Environments, Department of ECECS, University of Cincinnati
6.2 A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes
F. Vahid; Dept. of Computer Science, Univ. of California, U.S.A.
6.2 Fine-Grain, Incremental Rescheduling Via Architectural Retiming
Retiming; S. Hassoun; Dept. of Electrical Eng. and Computer Science, Tufts University
11:30 - 12:00Poster discussion
12:00 - 13:30Lunch
13:30 - 16:30Science-Based Industry Park tour
Saturday, December 5, 1998

Taipei City Tour

Sunday, December 6, 1998

Tarako National Park Tour

Final Program (Download Version)
  1. Microsoft Word 97 Version
  2. PostScript Version