邱𤅟德(Ching-Te Chiu) Associate Professor
Department of Computer Science
Institute of Communication Engineering
National Tsing Hua University,
Hsin-chu, Taiwan 30013, ROC
Tel: +886-3-573-1208,
Fax: +886-3-572-3694
E-mail:ctchiu@cs.nthu.edu.tw
URL:http://www.cs.nthu.edu.tw/people/faculty/ctchiu/index.htm
1992 Ph.D. (Electrical Engineering) University of Maryland, College Park
1988 M.S. (Electrical Engineering) National Taiwan University, Taipei, Taiwan
1986 B.S. (Electrical Engineering) National Taiwan University, Taipei, Taiwan
Multimedia system on chip (SOC) Design
High dynamic range image/video processing, Tone mapping,
Image enhancement IC
Video decoder designMulti core system on chip (SOC) platform
Software/Hardware codesign
Architecture OptimizationNetwork SOC design— High speed switch
SERDES
Gigabit IP traffic management,
SONET/SDH mapper/framer
ATM switch IC design
1. Promoting Academic Excellence of Universities Research Proposal
Sun-Project 1: High Speed Networking Technologies
2. Design and Implementation of High Dynamic Range Tone Mapping Processor in Surveillance Systems
Ching-Te Chiu received the B.S. and M.S. degree from National Taiwan University, Taipei, Taiwan, in 1986 and 1988 respectively. She received her Ph.D. degrees from University of Maryland, College Park, Maryland, USA, in 1992, all in electrical engineering.
She was an associate professor with National Chung Cheng University, Chia-Yi, Taiwan from 1993 to 1994. From 1994 to1996, she was member of technical staff with AT&T, Murry Hill, New Jersey, and at Lucent Technologies, Murry Hill New Jersey, from 1996 to 2000, and with Agere Systems, Santa Clara, California from 2000 to 2003. Since 2004, she has joined the Computer science department, National Tsing Hua University, Hsin-Chu, Taiwan.
She has been working on High Definition Television video decoder chip design, the standard television demodulation integrated circuit design, the SONET/SDH mapper and framer IC design, the ATM core/edge switch IC design, 10G I/P router traffic management design, and FEC decoder integrated circuit design.
Course
Network ASIC design –CS5250
http://nthucad.cs.nthu.edu.tw/~boki/cs5250
Fundamentals of Computer Science CS1356
Introduction to System-on-Chip and its Applications CS5151
Electronics and Circuits
Award
1. The first place award and the innovation award in the Macronix Golden Silicon Awards on “Loaded Balanced Birkhoff Von Neumann Symmetric TDM Switch IC.”指導老師：Ching-Te Chiu
獲獎學生：Hou-Cheng Tzeng, Yu-Hao Hsu2. 2006鳳凰盃設計競賽佳作 教育部大學院校矽智產設計競賽
指導老師：Ching-Te Chiu
獲獎學生：Hou-Cheng Tzeng, Yu-Hao Hsu3. CIC Digital IC Design Contests佳作
指導老師：Ching-Te Chiu
獲獎學生：Hou-Cheng Tzeng4. 教育部大學院校矽智產設計競賽 佳作
指導老師：Ching-Te Chiu
獲獎學生：Min-Sheng Kao
5. ARM-Code O-RAMA Hardware Design第一名
獲獎學生：柯瑋明
1. K. J. R. Liu, S. F. Hsieh, K. Yao, and C. T. Chiu, "Dynamic Range, Stability, and Fault-tolerant Capability of Finite-precision QRD RLS Systolic Algorithm," IEEE Trans. on Circuit and Systems, vol. 38, No. 6, pp. 625-636, June, 1991. (SCI/SSCI=5/208 , impact factor = , number of citation = 3, EI= )
2. C. T. Chiu, and K. J. R. Liu, "Real-Time Parallel and Fully-Pipelined Two-Dimensional DCT Lattice Structures with Application to HDTV Systems," IEEE Trans. on Circuits and Systems for Video Technology, Vol. 2, No. 1, pp. 25-37, March 1992. (SCI/SSCI=5/208 , impact factor = , number of citation = , EI= )
3. K. J. R. Liu, and C. T. Chiu, "Unified Parallel Lattice Structures for Time-Recursive DiscreteCosine/Sine/Hartley Transforms," IEEE Trans. on Signal Processing, Vol. 41, No. 3, pp. 1357-1377, March 1993. (SCI/SSCI=34/208 , impact factor = , number of citation =8 , EI= )
4. K. J. R. Liu, C. T. Chiu, R. K. Kolagotla, and J. F. J脃J脃, "Optimal Unified Architectures for the Real-Time Computation of Time-Recursive Discrete Sinusoidal Transforms," IEEE Trans. on Circuits and Systems for Video Technology , April, 1994. ((SCI/SSCI=34/208 , impact factor = , number of citation =8 , EI= )
5.C. T. Chiu, Yu-Hao Hsu, etc., “A Scalable Load Balance Birkhoff-von Neuman TDM Switch Fabric IC for High-Speed Networking Applications,” Submitted to IEEE Circuits and Systems, Part I, 2007.
6.Min-Sheng Kao, Chih-Hsien Jen, C.T. Chiu, etc., ``A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology,” submitted to IEEE transaction on Very Large Scale Integration Systems 2007.
7.H.J. Hsu, C.T. Chiu, Yarsun Hsu, “Design of Ultra Low Power Current-Mode Logics with Adaptive Body Bias,” Submitted to IEEE Transactions on Circuits and Systems, Part II, 2007.
Conferences
1. C. T. Chiu, R. Kolagotla, K. J. R. Liu, and J. F. J脃J脃,"VLSI implementation of Real Time Parallel DCT/DST Lattice Structures," Proceeding of IEEE workshop on VLSI Signal Processing, pp. 101-110, 1992.
2. K. J. R. Liu and C. T. Chiu, "Unified VLSI Lattice Architectures for Discrete Sinusoidal Transforms," Proceeding of the 35th Midwest Conference, Washington, DC, Aug. 1992.
3. C. T. Chiu, K. J. R. Liu, R.K. Kolagotla and J. F. J脃J脃, "Optimal VLSI Architectures for Time-Recursive Multidimensional Discrete Sinusoidal Transforms," Proceeding of Conference on Information Sciences and Systems, Baltimore, MD, March 1993.
4. K. J. R. Liu, C. T. Chiu, R.K. Kolagotla and J. F. J脃J脃,"Optimal Unified IIR Architectures for Time-Recursive Discrete Sinusoidal Transforms," Proceeding of IEEE ICASSP-93, MN, 1993.
5. C. T. Chiu, and K. J. R. Liu, "Real-Time Recursive Two-Dimensional DCT for HDTV Systems," IEEE ICASSP Proc., pp. III 205-208, March 1992.6. C. T. Chiu, and K. J. R. Liu, "Theoretical Analysis for Recursive Computation of Discrete Sinusoidal Transforms," IEEE Ten'con 94, Singapore, Aug., 1994.
7 .C. T. Chiu, and K. J. R. Liu, "Unified Lattice Architectures for Time-Recursive Discrete Sinusoidal Transforms with Applications to Real-Time Video Communications," Advances in VLSI Signal Processing 1994
8. C. T. Chiu, and K. J. R. Liu, "Parallel Implementation of Transformed-Based DCT Filter Bank for Video Communications," Proceeding of IEEE International Conference on Consumer Electronics, June 1994.
9.C.T. Chiu,Jen-Ming Wu Chun-Chieh Chang, ,etc.,” A 20Gbps Scalable Load-Balanced TDM Switch with CODEC for High Speed Networking Applications”IEEE IWSOC 2005, Banff Canada, July 2005.(NSC93-2752-E-007-002-PAE)
10. Min-Sheng Kao, Chih-Hsien Jen, C.T.Chiu, etc., ``A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology,” IEEE ISSOC 2005, Washington D.C., USA Sep 2005.(NSC93-2752-E-007-002-PAE)
11.C.T. Chiu, Hsiao Zen-Shiang, Chih-Hsien Jen, ‘’A 3.2Gb/s 20:1 CML Transmitter in 0.18 CMOS Technology’’, VLSI Design/CAD, 2005, Hau-Lien, Taiwan, Aug, 2005.(NSC93-2752-E-007-002-PAE)
12.Chih-Ying Tu, Cheng-Shang Chang, Duan-Shin Lee, and Ching-Te Chiu, ``Design a Simple and High Performance Switch Using a Two-stage Architecture,'' IEEE Globecom 2005, St. Louis, Missouri, USA, Dec., 2005.(NSC93-2752-E-007-002-PAE)
13.David Svensson and C. T. Chiu, “ Robust Interconnect Design in Mixed Clock systems”, ECS 2005, Bratislava, Slovakia, Sep, 2005.(NSC94-2215-E-007-016)
14. C.H. Hsiao, M. S. Kao, C. H. Jen, Y. H. Hsu, P. L. Yang, C. T. Chiu, J. M. Wu, S. H. Hsu, Y. S. Hsu, “A 3.2Gb/s CML Transmitter with 20:1 Multiplexer in 0.18Um CMOS technology”, 13th International Conference Mixed Design of Integrated Circuits and Systems MIXDES, Poland, June 22~24, 2006.(NSC93-2752-E-007-002-PAE)
15. Hou-Cheng Tzeng, Ching-Te Chiu, “A Flexible Cross Connect LCAS for Bandwidth Maximization in 2.5G EoS”, 5th IEEE Symposium on Network Computing and Applications, pp. 243-246, July 2006, MA, USA. (NSC94-2215-E-007-016)
16. Yu-Hao Hsu, Hong-Yu Lin, Fanta Chen, Hung-Yu Lin, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu, “A Low Power 2.56/3.2 Gbps Dual Mode 16/20:1 Serial-Link Transmitter”, VLSI Design/CAD 2006, pp. 634-637, Hau-Lien, Taiwan, Aug, 2006. (NSC93-2752-E-007-002-PAE)
17.Hou-Cheng Tzeng, Ching-Te Chiu, “A Flexible Cross Connect LCAS for Bandwidth Maximization in 2.5G EoS”, VLSI Design/CAD 2006, pp. 33-36, Hau-Lien, Taiwan, Aug, 2006.(NSC94-2215-E-007-016)
18.Ming-Cheng Du, Ching-Te Chiu,“Real-Time User-select Video Streaming on a P2P Network,” IEEE 13th International Conference on Systems, Signals, and Image Processing, Hungary, Sep., 2006.(NSC94-2215-E-007-016)
19. Chih Hsing Lin and Ching-Te Chiu, "A 80-400MHz Wide Range Low Jitter DLL-Based Frequency Multiplier Using PMOS Active Load for Communication Applications", IEEE International Symposium on Circuits and Systems, New Orleans, USA, May 27-30, 2007.(NSC94-2215-E-007-016)
20.Ching-Te Chiu,Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yar-Sun Hsu, “A Scalable Load Balanced Birkhoff-Von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications”, IEEE International Symposium on Circuits and Systems, New Orleans, USA, May 27-30, 2007. (NSC93-2752-E-007-002-PAE)
21.Tsun-Hsien Wang, and Ching-Te Chiu, “Low Power Design of High Performance Memory Access Architecture for HDTV Decoder”, IEEE International Conference on Multimedia and Expo, pp. 699-702, Beijing, China, July 2-6, 2007. ( NSC 95-2220-E-007-033).
22. Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu , Ming-Hao Lu, Ping-Lin Yang, You-Hung Li, Fanta Chen, Yu-Hao Hsu,Min-Sheng Kao, “A Quarter rate 2.56/3.2 Gbps 16/20:1 SERDES Interface in 0.18mm CMOS technology,” VLSI Design/CAD 2007, pp. 634-637, Hau-Lien, Taiwan, Aug, 2007. (NSC94-2752-E-007-002-PAE)
23. Tsun-Hsien Wang, Wei-Ming Ke, Ding-Chuang Zwao , Fang-Chu Chen, and Ching-Te Chiu, “Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video,” VLSI Design/CAD 2007, Hau-Lien, Taiwan, Aug , 2007. (NSC 95-2220-E-007-033).
24.Tsun-Hsien Wang, Wwi-Su Wong, Fang-Chu Chen, and Ching-Te Chiu, “Block-Based Gradient Domain High Dynamic Range Compression Design for Real-Time Implementations,” VLSI Design/CAD 2007, Hau-Lien, Taiwan, Aug, 2007. ( NSC 95-2220-E-007-033).
25. Tsun-Hsien Wang, Wei-Ming Ke, Ding-Chuang Zwao , Fang-Chu Chen, and Ching-Te Chiu, “Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video,” IEEE International Conference on Image Processing, VI, pp.209-212, San Antonio, TX, USA, Sep. 16-19, 2007. (NSC 95-2220-E-007-033).
26. Tsun-Hsien Wang, Wwi-Su Wong, Fang-Chu Chen, and Ching-Te Chiu, “Block-Based Gradient Domain High Dynamic Range Compression Design for Real-Time Implementations,” IEEE International Conference on Image Processing, San Antonio, TX, USA, Sep. 16-19, 2007. (NSC 95-2220-E-007-033).
27. H.J. Hsu, C.T. Chiu, Yarsun Hsu, “Design of Ultra Low Power CML MUXs and Lacthes with Forward Body Bias,” IEEE20th International SOC Conference, pp. 141-144, Hsinchu, Taiwan, Sept. 26-29, 2007. (NSC93-2752-E-007-002-PAE).
28. Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, and Shuo-Hung Hsu, “A 20Gbps scalable load balanced Birkhoff-von Neumann symmetric TDM switch IC with SERDES interfaces,” IEEE proceedings of the 12th Asia and South Pacific Design Automation Conference, pp. 23-26, Yokohama, Japan, 2007. (NSC-95-2752-E-007-002-PAE).
Book Chapter
Technical Report