*Q1:
1. SOC上的TAM bus與BIST engine的個數是否有限制??若有限,則各為多少??

2. 題目p.3的System description裡, Resource rsc1 rsc2只算BIST engine個
   數, 還是包含BIST circuitry??

3. 題目p.5的Examples裡, core_3的BIST宣告沒有指明使用rsc1或rsc2是否表示
   此core擁有BIST circuitry??

4. external test和BIST test都可以preemption嗎??

5. core所分配的bus是否可以改變??以題目p.6的Fig.2來說, core_3/ext_3所分
   配到的bus為[8:15], 假設ext_3在測試期間被中斷(preemption), 當ext_3再重
   新開始測試時, bus的配置是否可以改變(例如分配[16:23])??

*A1:
1. It is described in the SYSTEM description. TAM_width is the total TAM
   bus width.

2. Yes, number of BIST engines.

3. yes. core_3 in this example uses its own BIST resources.

4. Yes.

5. No, they will stay the same.

====================================================================
*Q2:
(1)在Input File中,system specification的precedence 
   只能寫成test1>test2這類型式,或是亦能寫成test2<test1的形式呢?? 
   (也就是能允許'<'的存在嗎?) 
(2)之前發問的問題中,指明core的BIST test能preemption,但BIST test被 
   preemption,這個core的external test依然不能先做,試問BIST test能 
   preemption的合理性何在?? 


*A2:
(1)
Only > precedence to make things simple.

(2)
Power consumption reason.

====================================================================
*Q3:
請問：
如果欲測試的Core有Multiple Bist Tests，那麼那些 Tests是否會
來自於不同的Bist Resources。即是：
Core 1
Bist test1 use Bist 1
Bist test2 use Bist 2
是否會有這種情況出現？


*A3:
+-!!WRONG ANSWER!!PLEASE REFER TO Q6---------------------+
|In real life design, this is not likely to happen.      |
|For this problem, we will assume this will not happen.  |
+--------------------------------------------------------+
====================================================================
*Q4:
能否說明一下，各項目評分所佔的百分比。

*A4:
Let's say basic requirement 85 %
Bonus : preemptive schedule + GUI 15%

====================================================================
*Q5:
如果一個Core裡同時具有Multiple External tests和Multiple BIST 
tests，那麼同一個core裡每個External test的power是否都會相同，
同樣地，同一個core裡每個BIST test 的power是否也會相同。謝謝。

*A5:
They can be different.

====================================================================
*Q6:
請問：
如果欲測試的Core有Multiple Bist Tests，那麼那些 Tests是否會
來自於不同的Bist Resources。即是：
Core 1
Bist test1 use Bist 1
Bist test2 use Bist 2
是否會有這種情況出現？

*A6:
Yes
====================================================================
*Q7:
先前問的問題中指明：某個Core裡面若存在Mutiple BIST tests
，這些BIST tests 可以來自於不同的BIST Resources。

Q1：
因為不同的Cores的pin可能不同，若允許同一個Core裡
的Mutiple BIST tests來自不同的BIST Resources，這樣不
是會增加routing的複雜度，還需要額外的控制電路來控制
哪些test是傳到哪個Core。請問允許同一個Core裡的
Mutiple BIST tests來自不同的BIST Resources的合理性？

Q2：
不同的BIST裡LFSR產生的random pattern可能會不同，若允
許BIST tests來自不同的BIST Resources，是否能保証能測出
所有的fault，沒有fault converage的問題。

*A7:
Consider two cores C1 and C2. C1 and C2 both contain module M1 and M2.
It is possible that we will have 2 bist resources Bist1 and Bist2 to test M1
and M2 respectively. So in this case, C1 and C2 has multiple BIST tests and
the BIST resources are different. This also answer Q2 above.


====================================================================
*Q8:
1.If a core has both BIST and external tests, the BIST tests must 
be performed prior to external tests. The user may also specify that 
one test must be executed before another. (The order of the BIST or 
external tests of the same core can be specified this way.)

是否代表若特別指定(precedence)，External tests can be performed 
prior to BIST tests ?

*A8:
No, a core BIST tests must always be performed before the external tests.

====================================================================
*Q9:
   在大會之前回答的問題(Q1.4)提到external test與BIST test皆可preemption,但在input file中只有提及external test的敘述可以出現
    preemption字樣(eg. External test_1 length 200 power 2 preemption 2), 而BIST test卻未提及, 這樣是代表BIST test可以被preemption無限多次嗎??
    還是會類似External test會出現能夠被preemption的最大次數呢??
*A9:
If a BIST test has preemption, it be be described similarly as in
External test.
No preemption is allowed If it is not specified.

e.g.
BIST test_3_2_1 length 629 power 45 premption 2


====================================================================
*Q10:
   之前發問的問題中,指明core的BIST test能preemption,但BIST test被 
   preemption,這個core的external test依然不能先做,試問BIST test能 
   preemption的合理性何在?? 

*A10:
Maybe power issue.

====================================================================
*Q11:
      請問同一個core 裡不同的 External test 所分配到的 pin 腳是否要相同?
       如下列情況:
                         core_a  的 test_1 分配到 [0:5]
                         test_2 分配到 [5:10]
        是否符何題意?
 
        如果符合題意的話, output format 在題目中似乎沒有明確規範.
        (針對同一個 core 不同的 external test 該如何在 output file 表示所分配
        到的pin 腳?)


*A11:

The TAM assignment is for a core, not individual test of a core. So if a
core have
multiple external tests, you only have to specify the TAM assignment for
the core.
====================================================================
*Q12:
如果有一個core的bist和external如下圖所示
 
此core並沒有external test
 
那是否output file中的： TAM_assignment core_5就省略？
 
##### Core 5 #####
Core core_5
begin
 TAM_width 68
 BIST  test_5_1_1 length 666 power 5
 BIST  test_5_1_2 length 769 power 68
 BIST  test_5_1_3 length 171 power 22
 BIST  test_5_1_4 length 474 power 47
 BIST  test_5_1_5 length 807 power 65
 BIST  test_5_1_6 length 265 power 60
end


*A12:
If there is no external test, the TAM width should be 0 in the core
description.
Yes, the TAM assignment is left empty if there is no external test and
the TAM
width is 0.

====================================================================